Wireless MAC Design Engineer Apple IncWireless MAC Design EngineerSunnyvale, CACome join Apple's wireless silicon development effort, with its emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically coordinated engineering team. Develop MAC layer design for wireless communication SoCs, including creating microarchitecture and other documents based on system-level requirements, and writing area- and power-efficient RTL that is scalable.
Physical Design Engineer Ambarella IncPhysical Design EngineerCA$140,000–$156,000 / yearThe Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level. The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella's cutting edge low power AI SoC from Netlist to GDSII.
Electrical Engineer - Integrated Analog/Digital Design Level 3 /4 Northrop Grumman CorpElectrical Engineer - Integrated Analog/Digital Design Level 3 /4Sunnyvale, CA$114,000–$171,000 / yearThe Launcher Electronics group is seeking an Electrical Engineer - Integrated Analog/Digital Design Level 3 /4 with knowledge and experience with design and test of analog and digital circuitry, cable design, data acquisition systems, and electronic control systems including motors, mechanical actuators, and sensors. We are looking for you to join our Launcher Electronics Group as an Electrical Engineer - Integrated Analog/Digital Design Level 3 /4 for the development and ongoing support of new and existing electrical designs used in surface ship and submarine launch control systems for the US Navy located in Sunnyvale, CA.
Senior Principal Digital Design Engineer Astera Labs IncSenior Principal Digital Design EngineerSan Jose, CA$205,000–$255,000 / yearThis is a high-impact technical leadership role where youll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. As a senior technical leader, youll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon.
Tech Lead Design Engineer Astera Labs IncTech Lead Design EngineerSan Jose, CA$133,200–$185,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Digital Design Engineer Astera Labs IncPrincipal Digital Design EngineerSan Jose, CA$185,000–$230,000 / yearYoull own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the worlds leading hyperscalers.
ASIC Design Engineer - Pixel IP Apple IncASIC Design Engineer - Pixel IPSunnyvale, CAApply your knowledge of computer architecture and digital design to create digital signal processing pipelines for capturing, improving, compressing, decompressing, and displaying digital still images and video. In this front-end design role, your tasks will include: Design digital hardware by writing high-quality RTL or using a high-level synthesis methodology, with embedded assertions and cover points.
NewAnalog Design Engineer OmnivisionAnalog Design EngineerSanta Clara, California$156,853–$160,000 / yearDesign analog building blocks such as Analog Static RAM (ASRAM), ensuring support for complex readout formats including Dual Conversion Gain (DCG), Correlated Double Sampling (CDS), Correlated Multiple Sampling (CMS), and 4c2p. Requirements: Master’s degree in Electrical Engineering, Computer Engineering, or a related field with advanced-level courses work in Analog Integrated Circuit, CMOS Circuit Design, RF Circuits and Systems Design, VLSI system design, and VLSI Signal Processing.
Digital Design Director Ford Motor CoDigital Design DirectorPalo Alto, CA$167,200–$316,600 / yearWe do this through bringing the right cross-functional teams and right skillsets together early, identifying key hardware and software technology and connections needed to unblock and deliver incredible experiences to each of our unique customer groups. Rather than focusing on one-off feature-driven solutions, this team moves up stream to get ahead of delivery cycles, building bridges through curiosity and a clear mission to deliver on our brand equities and core customer needs.
2027 Undergrad Hardware Design Verification Engineering Co-op/Intern Advanced Micro Devices Inc2027 Undergrad Hardware Design Verification Engineering Co-op/InternSanta Clara, CAWHAT YOU WILL BE DOING: We are seeking a highly motivated Hardware Design Verification Engineering intern/co-op to join our team and work towards design, built, and delivery of AMD's high-end Machine Intelligence products. You'll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide.
2027 Masters Hardware Design Verification Engineering Co-op/Intern Advanced Micro Devices Inc2027 Masters Hardware Design Verification Engineering Co-op/InternSanta Clara, CAWHAT YOU WILL BE DOING: We are seeking a highly motivated Hardware Design Verificaon engineering intern/co-op to join our team and work towards design, built, and delivery of AMD's high-end Machine Intelligence products. You'll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide.
Sr. Staff GaN Device Design Engineer Alpha & Omega SemiconductorSr. Staff GaN Device Design EngineerSunnyvale, CAFull timeAt Alpha and Omega Semiconductor (AOS), we design, develop and globally supply a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM, TVS, GaN/SiC, Power IC and Digital Power products. You will find our products in everyday applications including personal computers, graphic cards, gaming consoles, TVs, home appliances, smart phones, power tools, and more!
Principal Engineer, ASIC Design Verification Ayar Labs IncPrincipal Engineer, ASIC Design VerificationSan Jose, CA$190,000–$240,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Strategic Planning: Collaborate with Architects and RTL Designers early in the cycle to define the verification plan, identify architectural bottlenecks, and ensure micro-architecture testability.
Design Characterization Engineer Omnivision TechnologiesDesign Characterization EngineerSanta Clara, CA$110,600–$140,000 / yearWork cross‑functionally with process, applications, production, and quality teams to transition new designs into production and resolve yield, reliability, and overall product quality issues. In this role, you will characterize and optimize CMOS image sensor performance, collaborate closely across engineering disciplines, and help deliver industry‑leading sensor products with exceptional quality.
Graphics Cache Hierarchy Design Verification Engineer Apple IncGraphics Cache Hierarchy Design Verification EngineerSanta Clara, CAThe Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects and Link interface units. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.
CPU Design Timing Engineer Apple IncCPU Design Timing EngineerSanta Clara, CAWork extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.Minimum BS and 3+ years of relevant experience Experience with static timing analysis, noise analysis, and fixing noise in designs Experience with variation modeling Experience with TCL and either Perl or PythonPrior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs Experience in a static timing analysis tool such as PrimeTime/Tempus Knowledge of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron technologies and scaling trends Working knowledge of CPU microarchitecture Possess data parsing, analysis and representation/plotting skills. In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.
NewFPGA Design Engineer KLAFPGA Design EngineerMilpitas, CaliforniaOur designs employ cutting edge combination of low noise analog to highly complex digital signal circuits, which are enabling our leading technology in the advancing semiconductor industry. Our expert teams of physicists, engineers, data scientists and problem-solvers work together with the world’s leading technology providers to accelerate the delivery of tomorrow’s electronic devices.
PMTS ASIC Digital Design IP ENGINEERING GlobalFoundries IncPMTS ASIC Digital Design IP ENGINEERINGSanta Clara, CA$167,000–$275,000 / yearSummary of Role: The PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies.
Digital IC Design Engineer Intern NeuralinkDigital IC Design Engineer InternSouth San Francisco, CAJob Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces.
Digital Design Lead PhizenixDigital Design LeadSanta Clara, CA$180,000–$200,000 / yearThis role leads the digital design effort across high-speed interface and memory subsystem IPs, partnering with architecture, verification, and physical design teams to deliver silicon-ready designs. We are seeking experienced Digital Design Leads to drive RTL design and verification for next-generation semiconductor products.