Stability Quality Engineer - Data Center Systems Quality Apple IncStability Quality Engineer - Data Center Systems QualitySunnyvale, CADesign, develop, and execute system-level and rack-level stability and stress tests across data center platforms, validating functional and stress characteristics to ensure systems meet stability requirements Manage and operate racks of systems running concurrent tests, experiments, and long-duration workloads that simulate production deployment conditions Identify, reproduce, isolate, debug, and conduct root cause analysis on issues using performance analysis, debugging tools, and stress benchmarks that expose design flaws Partner cross-functionally with hardware, software, data center operations, and quality teams to identify risk areas specific to data center platforms and define comprehensive test strategies Develop and optimize test frameworks and tools to create controlled validation environments that support large-scale validation Report issues clearly using Apples bug reporting processes, support engineering investigations with data and technical analysis, and communicate findings to inform product readiness decisionsBachelors degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent degree 3+ years of experience in hardware/software test engineering with demonstrated focus on system validation or data center environments Hands-on experience with modern CPU architecture and microarchitecture concepts demonstrated through previous work on processor-level debugging or validation projects Proficiency with Unix-based operating systems and scripting automation using languages such as Python, Ruby, Swift, or JavaScript & experience developing or executing test automation frameworks and methodologies at scale Proven ability to design and execute comprehensive validation test plans, work independently and collaboratively with cross-functional engineering teams, and deliver results in concurrent multi-system environmentsMasters or PhD in Electrical Engineering, Computer Science, Computer Engineering, or equivalent degree Experience with hardware bring-up, debug, and troubleshooting in data center or server environments, including using stress tools and benchmarks, and factory processes such as burn-in or qualification testing Developed and maintained automation frameworks and tools that expand test coverage in complex system environments and support large-scale validation Experience with data visualization tools (such as Tableau) and AI-powered tools or agents for test development and data analysis. Working across multiple systems, youll design automated tests, collaborate with hardware and software engineering partners, and conduct deep technical investigations to identify and mitigate system-level risks in large-scale deployment environments.
Template Job Astera Labs IncTemplate JobSan Jose, CA$207,000–$230,000 / yearServe as the internal authority on fabric modeling, partnering with ASIC architects and product teams to drive roadmap and feature decisions, support early customer engagement, and produce modeling reports, white papers, and presentations for engineering, product, and executive audiences. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Staff Software Engineer - Compute Systems Software (Embedded OS) General Motors CoStaff Software Engineer - Compute Systems Software (Embedded OS)Mountain View, CA$217,000–$275,000 / yearYou'll work across the Linux kernel, board support packages (BSP), device drivers, and core frameworks on modern ARM-based SoCs, using C and classic UNIX/Linux tooling to deliver high-performance, highly reliable compute in production vehicles. You'll report to the Software Engineering Manager, Compute Systems Software, and collaborate closely with partners across Android Automotive OS, multimedia, connectivity, and system frameworks to deliver platform capabilities that scale globally across GM's vehicle portfolio.
Fabric Modeling And Analysis Engineer For Scale Up Fabric (2026-325) Astera LabsFabric Modeling And Analysis Engineer For Scale Up Fabric (2026-325)San Jose, CA$185,000–$240,000 / yearServe as the internal authority on fabric modeling, partnering with ASIC architects and product teams to drive roadmap and feature decisions, support early customer engagement, and produce modeling reports, white papers, and presentations for engineering, product, and executive audiences. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Server IO Specialist. Sr. Director of Technology Qualcomm IncServer IO Specialist. Sr. Director of TechnologySanta Clara, CA$284,900–$427,300 / yearMinimum Qualifications: Bachelor''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 10+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 9+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Server Project Engineer Qualcomm IncServer Project EngineerSanta Clara, CA$233,000–$349,600 / yearMinimum Qualifications: Bachelor''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Server SoC Security Architect - CCA Qualcomm IncServer SoC Security Architect - CCASanta Clara, CA$198,700–$298,100 / yearMinimum Qualifications: Bachelor''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Staff Engineer, Hardware Application Engineering - Lab Operations Marvell Technology IncStaff Engineer, Hardware Application Engineering - Lab OperationsSanta Clara, CAWorking familiarity with high-speed test and measurement equipment such as oscilloscopes, BERTs, VNAs, TDR, jitter analyzers, logic analyzers, power supplies, electronic loads, and compliance test kits - comfortable operating, configuring, and troubleshooting these instruments, with the ability to deepen expertise on specific tools as needed. Maintain dedicated RMA test setups used to examine field-returned chips - keep the systems, test programs, and instrumentation always ready to receive and process RMA units the moment they arrive, including ensuring proper test-hole-plug coverage and re-test readiness whenever needed.
DFT Design Engineering Director Astera LabsDFT Design Engineering DirectorSan Jose, CA$230,000–$265,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale.
Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity MarvellSenior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power IntegritySanta Clara, CaliforniaYou will own layout guideline definition, post-silicon channel extraction and simulation, compliance testing, and SerDes tuning guidance, while also reviewing customer PDN designs and feeding learnings back to Marvell's silicon and hardware engineering teams as part of a continuous improvement loop. Note on experience level: While the years of experience above represent the typical bar for this role, exceptionally talented candidates with fewer years but demonstrated mastery — through impactful project work, deep technical contributions, or industry recognition — are strongly encouraged to apply.
DFT Design Engineering Director Astera Labs IncDFT Design Engineering DirectorSan Jose, CA$230,000–$265,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. In this critical leadership role, you will define and execute the DFT strategy for complex, high-speed SerDes-based switching solutions, ensuring optimal testability, yield, and quality while enabling cost-effective manufacturing at scale.
Senior Principal Engineer, Hardware Application Engineering — Board & System Design MarvellSenior Principal Engineer, Hardware Application Engineering — Board & System DesignSanta Clara, CaliforniaYou will spend most of your time reviewing and shaping customer hardware designs — covering board architecture, PCB stack-up and material selection, power architecture, thermal design, mechanical integration, and reliability and retain full hands-on capability across the entire design lifecycle from architecture through schematic, layout guidance, and bring-up. As Senior Principal Engineer for Board & System Hardware Design, you will be the senior technical authority guiding customer hardware design-in on Marvell's Ethernet Switch and UALink platforms, and a key technical bridge between Marvell's silicon teams, internal hardware engineering, and the field.
Physical Design Engineering, VP Astera LabsPhysical Design Engineering, VPSan Jose, CA$250,600–$375,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Physical Design Engineering, VP Astera Labs IncPhysical Design Engineering, VPSan Jose, CA$250,600–$375,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Staff ASIC Design Verification Engineer Google LLCStaff ASIC Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future.
Staff Silicon Architect, DeepMind Google LLCStaff Silicon Architect, DeepMindMountain View, CAIn this role, you will bring expertise spanning hardware, including architecture, logic design, design verification, and physical design software, such as compilation, performance optimization, libraries, operating systems, and kernels, and algorithms, covering ML model design, optimization methods, numerics, and sparsity. In this role, you will help deliver codesigned systems that, unlike classic data center infrastructure, must meet future demands as our workloads continue to evolve and mutate.
TPU Validation Manager Google LLCTPU Validation ManagerMountain View, CALead and manage the team responsible for the silicon validation of Tensor Processing Unit (TPU), Google"s custom machine learning accelerator, in mobile SoC products. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
TPU Hardware Design Engineer, Cloud Google LLCTPU Hardware Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You will join the team designing and developing the on-chip network of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
Senior TPU Validation Engineer Google LLCSenior TPU Validation EngineerMountain View, CAGoogle is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Minimum qualifications: Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
Silicon Physical Design Engineer Google LLCSilicon Physical Design EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.