Keywords: ASIC architecture, packet processing pipelines, hardware network protocols, RTL design, Verilog, SystemVerilog, high-speed networking, protocol offload engines, Network-on-chip, P4, programmable data planes, HBM, DDR, SRAM, TCP/IP, RoCE, NVMe-of, load balancing, QoS, NFV, L2 switching, L3 switching, L4 switching, routing, MACsec, ethernet MAC/PHY integration. Qualifications for the Packet Processor Architect include: 15+ years of experience in networking or data-path ASIC architecture and design, with a proven track record in architecting packet-processing engines in high-throughput ASICs or SoCs.