The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5. You will also be eligible for equity and benefits. As a Solutions Architect, you will serve as a key technical expert bridging NVIDIA’s ground breaking GPU and NVLink technology designs as well as all of our software solutions directly between engineering and field teams supporting customers with the most demanding requirements.
p>Job Description: Hiring a talent in advanced packaging design with intensive hands-on experience in GDSII-based physical layout and in-depth knowledge in advanced 2.5D/3D packaging architect and technology.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Us, California30+ days ago
The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5. You will also be eligible for equity and benefits. In this role, you will be at the forefront of assisting with designs and architectures for next-generation networking solutions that connect thousands of GPUs and enable the world’s most advanced AI supercomputers and enterprise AI infrastructure in the field.
p>Responsibilities include: • Develop channel models and run simulations to help define Serdes architecture • Define and document signal processing block requirements, architecture, and lab test plan • Develop bit-exact MATLAB and C/C++ system models for simulation and verification • Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs • Work with the design team to perform vector matching verification with RTL simulations • Develop, test, and debug firmware associated with physical layer functionality • Lab testing and debug of Serdes • Documentation/application note development and customer support • Support marketing group with customer meetings and collateral. plus 6 years required • Expert knowledge in Communication Theory • Expert knowledge in Digital Signal Processing algorithms • Working knowledge of Analog circuit behavior • Working knowledge of Transmission line theory and s-parameter • Expert in MATLAB, C/C++ programming • Good hands-on skills in the lab • Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.
San Francisco, CA9 days ago
You''ll manage a talented team of Store Designers that''s united in beauty, supported by those who are equally passionate about creating beautiful, functional, and cost-effective stores that elevate the Sephora experience. What You''ll Do:
- Coach, lead, and inspire a high-performing team of Store Designers, providing guidance through design challenges, layouts, and storefront design while fostering a culture of collaboration and growth.
p>Candidates should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment. One aspect of the process is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best power interconnect.
Us, California25 days ago
You will work with world-class AI researchers, silicon architects, and AV platform teams to identify the AI workloads that will define the next decade — and ensure NVIDIA platforms are architected to lead them. Experience mapping AI workloads onto heterogeneous compute architectures including GPUs, CPUs, NPUs/DLAs, DSPs, and memory subsystems.
Santa Clara, CA24 days ago
You will work with world-class AI researchers, silicon architects, and AV platform teams to identify the AI workloads that will define the next decade - and ensure NVIDIA platforms are architected to lead them. We are looking for a Senior AI Architect to help define the next generation of AI model paradigms for autonomous vehicles and shape how those models co-evolve with NVIDIA's future embedded SoC architectures.
Los Angeles, CA2 days ago
The role offers a competitive salary ranging from $75,000 to $115,000 and a variety of benefits including health insurance and a flexible schedule.#J-18808-Ljbffr. Ideal applicants will also understand IBC/CBC codes and have hands-on experience with construction types I, III, and V.
Sunnyvale, CA30+ days ago
You Are: You are a visionary engineering leader with deep expertise in FPGA design and advanced protocol integration, ready to architect and deliver solutions that bridge real-world interfaces with cutting-edge emulation and prototyping platforms. The team collaborates globally across IP, emulation, and prototyping domains to deliver robust, high-performance system validation solutions, directly impacting the success of top semiconductor and hyperscale customers.
This team builds the critical bridge between Synopsys' ZeBu emulation and HAPS prototyping platforms and the real-world devices, testers, and hosts that customers need to connect to their pre-silicon designs. The team works closely with IP teams developing PCIe, CXL, UCIe, and other high-speed protocols, as well as with emulation and prototyping platform engineers to deliver integrated system-level validation solutions.
Los Angeles, California30+ days ago
The Design Advocate is the structural fix and is embedded close enough to Product to understand what’s coming, while proactively ensuring Sales, Marketing, and CS are fully prepared before launches happen. This person sits at the intersection of Product, Sales, Marketing, and Customer Success, serving as Pirros’ in-house practitioner voice and strategic bridge between Product and GTM teams.
Experience is highly preferred in end-to-end development of startup/GPU AI hardware, including programming models, GPU microarchitectures, tapeout, and bring-up. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Palo Alto, CA30+ days ago
p>Strong background in fault-tolerant quantum computing, with experience in some of the following areas strongly preferred: • Linear optical quantum computing • Quantum error correction • Quantum networks • Error modelling • Switching / multiplexing networks • Error modelling • Graphical calculus (e.g., tensor networks, ZX calculus). Our application, software, and industry teams work directly with leading Fortune 500 companies-including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical-to prepare quantum solutions for real-world impact.