NewHardware Design Engineer 4 ObjectWin TechnologyHardware Design Engineer 4San Jose, CATHE ROLE:As a member of the CT Server DDR team, we are looking for an experienced signal integrity and power integrity engineer who can be responsible for DDR PHY channel and power delivery network (PDN) architecture, system-level SI/PI, and post-silicon validation. KEY RESPONSIBILITIES: Run system-level channel and PDN simulations (insertion/return loss, crosstalk, eye diagrams, impedance, IR drop, jitter transfer) and correlate with silicon results.
Senior Design Engineer - Actuators Rhoda AISenior Design Engineer - ActuatorsMountain View, CaliforniaTest Plan Definition: Partner with modeling and test engineers to define test plans for optimization and durability of your components — characterization runs, life tests, environmental tests, and the failure-mode-specific tests that catch the issues a generic protocol misses. You translate system-level targets into manufacturable hardware, working hand-in-hand with modeling and test engineers to make sure the parts you draw are sized correctly, behave as predicted, and survive the duty cycles our robots see in the real world.
Mechanical Design Engineer - Onsite SJC (6219) itDMechanical Design Engineer - Onsite SJC (6219)San Jose, CaliforniaPerform detailed 2D tolerance analysis for complex electro-mechanical assemblies• Assist with resolution of design related issues that are impacting field or manufacturing by working closely with manufacturing teams and suppliers, developing mitigation plans, and keeping management informed.• Strong knowledge of sheet metal, plastic, and die-cast tooling Preferred Skills: • Relevant experience in the mechanical design of computer/network equipment designed to operate in data centers is preferred.•
ASIC Design Engineer – DSP / Analog / SerDes Celero CommunicationsASIC Design Engineer – DSP / Analog / SerDesSan Jose, California$150,000–$250,000 / yearCelero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. • Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
Interconnect Design Engineer SiFiveInterconnect Design EngineerSanta Clara, CA$205,740–$251,460 / yearSiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. Job Description: The Role: SiFive is looking for a senior staff level hardware engineer who is passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications.
RTL / Physical Design Engineer PersimmonsRTL / Physical Design EngineerSan Jose, CABuild and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes—leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation.
ASIC Design Engineer Technical Lead CiscoASIC Design Engineer Technical LeadSan Jose, CaliforniaThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $186,900.00 - $307,800.00 Non-Metro New York state & Washington state: $166,300.00 - $274,100.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design experience.
IC Package Design Engineer CiscoIC Package Design EngineerSan Jose, CaliforniaThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $152,500.00 - $252,000.00 Non-Metro New York state & Washington state: $135,800.00 - $224,400.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.
Physical Design Engineer - Flow & Methodologies EtchedPhysical Design Engineer - Flow & MethodologiesSan Jose, CaliforniaYou will own the infrastructure that allows our design team to iterate at unprecedented speeds, directly accelerating our time-to-market and enabling PPA gains that aren't possible with off-the-shelf CAD methodologies. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Analog/mixed-signal IC Design Engineer - Acacia (Hybrid) CiscoAnalog/mixed-signal IC Design Engineer - Acacia (Hybrid)San Jose, CaliforniaThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $171,600.00 - $281,800.00 Non-Metro New York state & Washington state: $151,300.00 - $250,900.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G, 800G and 1.6T+ bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.
Design Verification Engineer, Silicon GoogleDesign Verification Engineer, SiliconMountain View, CADevelop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios.
ASIC Design Verification Engineer, TPU GoogleASIC Design Verification Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Silicon Design Verification Engineer GoogleSilicon Design Verification EngineerMountain View, CADevelop and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
Product Design Engineer V || Cupertino, CA (Onsite) Pride GlobalProduct Design Engineer V || Cupertino, CA (Onsite)Cupertino, CA$4,477.60 / weekThis applies to direct care staff (Examples: RN, LPN, Nurse Aides, Therapists) referred to Kentucky nursing facilities, assisted living communities, or long-term care facilities, in accordance with KRS 216.793. Only applicable for San Francisco Candidates : Under the San Francisco Lactation in the Workplace Ordinance, we will provide written notice of lactation accommodation rights, and this notice will automatically be given upon hiring, any inquiry of parental leave or lactation accommodation.
Integration RTL Design Engineer Advanced Micro Devices, IncIntegration RTL Design EngineerSan Jose, CaliforniaFull ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation. RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
Design Verification Engineer - Physical AI Compute Velaura AI IncDesign Verification Engineer - Physical AI ComputeSunnyvale, CAStaff / Principal)On-site - Full-timeBangalore / Santa Clara, CADVApplyDesign Verification EngineerOn-site - Full-timeSanta Clara, CA / Austin, Texas / Boston, MAApplyDesign Verification Engineer- AI Accelerator LeadOn-site - Full-timeSanta Clara, CAApplyDesign Verification Engineer- CPUOn-site - Full-timeSanta Clara, CAApplySenior Design Verification EngineerOn-site - Full-timeSanta Clara, CAApplySenior Formal Verification EngineerOn-site - Full-timeSanta Clara, CAEmulationApplySenior Emulation EngineerOn-site - Full-timeSanta Clara, CAPerformanceApplyPerformance Modeling Architect - AI SystemsOn-site - Full-timeDurham, North Carolina / Santa Clara, CA / Boston, MA / Austin, TexasRTLApplyRTL DesignerOn-site - Full-timeSanta Clara, CAApplyRTL LeadOn-site - Full-timeSanta Clara, CAApplyRTL Power EngineerOn-site - Full-timeSanta Clara, CAApplySenior RTL EngineerOn-site - Full-timeSanta Clara, CASoftwareCompiler & ToolchainApplyAccelerator Compiler and Tool Chain LeadOn-site - Full-timeSanta Clara, CAPlatform SoftwareApplyPlatform Software Lead - Physical AIOn-site - Full-timeSanta Clara, CAApplyPrincipal AI SoC Runtime Software ArchitectOn-site - Full-timeSanta Clara, CA. Manager)On-site - Full-timeBangalore / Santa Clara, CAApplyPhysical Design Engineer (Staff / Sr.
Senior Design Verification Engineer - Physical AI Compute Velaura AI IncSenior Design Verification Engineer - Physical AI ComputeMenlo Park, CAStaff / Principal)On-site - Full-timeBangalore / Santa Clara, CADVApplyDesign Verification EngineerOn-site - Full-timeSanta Clara, CA / Austin, Texas / Boston, MAApplyDesign Verification Engineer- AI Accelerator LeadOn-site - Full-timeSanta Clara, CAApplyDesign Verification Engineer- CPUOn-site - Full-timeSanta Clara, CAApplySenior Design Verification EngineerOn-site - Full-timeSanta Clara, CAApplySenior Formal Verification EngineerOn-site - Full-timeSanta Clara, CAEmulationApplySenior Emulation EngineerOn-site - Full-timeSanta Clara, CAPerformanceApplyPerformance Modeling Architect - AI SystemsOn-site - Full-timeDurham, North Carolina / Santa Clara, CA / Boston, MA / Austin, TexasRTLApplyRTL DesignerOn-site - Full-timeSanta Clara, CAApplyRTL LeadOn-site - Full-timeSanta Clara, CAApplyRTL Power EngineerOn-site - Full-timeSanta Clara, CAApplySenior RTL EngineerOn-site - Full-timeSanta Clara, CASoftwareCompiler & ToolchainApplyAccelerator Compiler and Tool Chain LeadOn-site - Full-timeSanta Clara, CAPlatform SoftwareApplyPlatform Software Lead - Physical AIOn-site - Full-timeSanta Clara, CAApplyPrincipal AI SoC Runtime Software ArchitectOn-site - Full-timeSanta Clara, CA. Manager)On-site - Full-timeBangalore / Santa Clara, CAApplyPhysical Design Engineer (Staff / Sr.
Lead Design Engineer StepLead Design EngineerSan Mateo, CARemoteYou'll partner closely with Product Design and Engineering leadership to evolve our design platform, reduce friction in the product development process, and create a future where moving from an idea to production is faster, more reliable, and nearly lossless. Beast Industries spans digital media, consumer products, philanthropy, and new ventures, with an audience reach no consumer company has ever had — and Step is tasked with turning that reach into financial literacy and tools for the next generation at massive scale.
Sr. Design For Test (Dft) Engineer LightmatterSr. Design For Test (Dft) EngineerMountain View, CA$164,000–$185,000 / yearPreferred Qualifications: Master degree in Electrical Engineering, Computer Engineering, or related field with 3+ years of industry experience working on ASIC designs with multiple production-quality ASIC tapeouts. The company invented the world's first 3D-stacked photonics engine, Passage, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads.
Sr. Engineer, Photonics Device Design Ayar LabsSr. Engineer, Photonics Device DesignSan Jose, CaliforniaAs a photonics design engineer at Ayar Labs, you'll work on the devices at the heart of our CPO solution — designing, simulating, and characterizing integrated photonic components for an aggressive optical I/O product roadmap. Backed by industry leaders including NVIDIA, AMD, MediaTek and Intel, our technology moves data at the speed of light — faster, further, and with a fraction of the energy consumed by conventional electrical interconnect.