NewPackaging Operator Lancesoft INCPackaging OperatorNewark, CACandidates should be aware that there may be active picketing and strike-related activity outside the facility, which can create a less favorable or less peaceful environment when entering and exiting the site. Running bagging machine to ensure the correct animal feed makes it into the correct bags in a safe and quality-oriented manner.
Packaging Operator Lv3 Apidel TechnologiesPackaging Operator Lv3NEWARK, CAContractorCandidates should be aware that there may be active picketing and strike-related activity outside the facility, which can create a less favourable or less peaceful environment when entering and exiting the site. Running bagging machine to ensure the correct animal feed makes it into the correct bags in a safe and quality-oriented manner.
Advanced Package Engineer, Principal Astera LabsAdvanced Package Engineer, PrincipalSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Silicon Photonics PIC Design Engineer Broadcom CorporationSilicon Photonics PIC Design EngineerSan Jose, CA$143,800–$230,000 / yearAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components that power our high-performance optical interconnect solutions.
SI/PI Engineer Danta TechnologiesSI/PI EngineerSunnyvale, CA$50–$65 / hourIn this role, you will be responsible for signal integrity and power integrity analysis, modeling, and design optimization of next-generation multi-die packaging architectures including 2.5D/3D integration, silicon interposers, and high-bandwidth memory (HBM) interfaces. Perform time-domain simulations (eye diagram, BER analysis) for high-speed serial and parallel interfaces (PCIe Gen5/6, UCIe, HBM3/3E, DDR5, SerDes >112 Gbps).
NPI Product Engineer KLA CorporationNPI Product EngineerMilpitas, CA$95,000–$161,500 / yearOur comprehensive services include: proactive management of tools to identify and improve performance; expertise in optics, image processing and motion control with worldwide service engineers, 24/7 technical support teams and knowledge management systems; and an extensive parts network to ensure worldwide availability of parts. The KLA Services team headquartered in Milpitas, CA is our service organization that consists of Service Sales and Marketing, Spares Supply Chain management, Field Operations, Engineering, Product Training, and Technical Support.
Director, AI Governance & Privacy Attorney KLA CorporationDirector, AI Governance & Privacy AttorneyMilpitas, CA$207,300–$362,800 / yearThe Legal Compliance Organization (LCO) team headquartered in Milpitas, CA and second headquarters in Ann Arbor, MI provides legal guidance to further KLA's strategic objectives and protect and preserve the legal, ethical and financial integrity and reputation of the Company. With specific expertise in the areas of corporate law, commercial law, employment law, and intellectual property; the LCO offers strategic legal counsel that is informed by a clear understanding of the company's business objectives and expertise in the laws and regulations relevant to the business worldwide.
Package Engineer Delos DataPackage EngineerPalo Alto, CaliforniaSelect and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Director Of Test - Silicon Photonics MarvellDirector Of Test - Silicon PhotonicsSanta Clara, CAStrong experience in system level test plan definition and execution, preferably for transceiver products involving systems with DSP/TIA/Driver with PICs, and high-speed (56 Gbps+/lane) measurement such as BER testing, eye-diagram analysis, and S-parameter characterization. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Senior Mechanical Hardware Engineer – ECU Connectors & Interfaces GMSenior Mechanical Hardware Engineer – ECU Connectors & InterfacesSunnyvale, California$125,200–$192,700 / yearCoordinate closely with electrical engineers and PCB designers on connector pinout constraints, PCB attachment strategy, soldering or alternate mounting concepts, grounding paths, shielding interfaces, and packaging of high-speed and power connections into complete electromechanical systems. Own mechanical design of connector-related content from concept through production release, including connector housings, integrated or discrete headers, terminal retention features, bus bar interfaces, seals, gaskets, and attachment features to the ECU housing.
Principal Signal & Power Engineer (Die to Die and Chiplet Design) Microsoft CorpPrincipal Signal & Power Engineer (Die to Die and Chiplet Design)Mountain View, CA$142,800–$274,800 / yearDrives the execution of architecture solutions across product lines or multiple product groups across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry best practices, and lessons learned from teams working across multiple product lines. IP design, voltage regulator, motherboard, CPU package, silicon, decoupling capacitor solutions, dielectric and copper loss, high-frequency discontinuities, timing budgets, power supply induced jitter, etc.) for data center processors and corresponding platforms to ensure optimized performance.
R&D Engineer IC Design Broadcom CorporationR&D Engineer IC DesignSan Jose, CA$120,000–$192,000 / yearStrong automation expertise related to bump pattern generation, routing structure development for high speed interfaces, and chip finishing are required to handle multiple Interposer designs in parallel. You will be working on designing interposers starting with custom routing for high speed interfaces, bump map design, routing and physical verification and tapeout to the foundries.
Advanced Package Design Engineer SK hynixAdvanced Package Design EngineerSan Jose, CA$110,000–$155,000 / yearOur cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies.
Advanced Package Design Engineer SKHYAAdvanced Package Design EngineerSan Jose, California$110,000–$155,000 / yearOur cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies.
Senior Laser & SOA Characterization Engineer LightmatterSenior Laser & SOA Characterization EngineerMountain View, CA$210,000–$267,000 / yearExperience operating optical and RF instruments, including laser current drivers, TEC controllers, OSAs, optical power meters, photodetectors, RF spectrum analyzers, oscilloscopes, bias tees, optical filters, polarization controllers, optical switches, and fiber-coupled components. In this role, you will lead advanced characterization, bring-up, validation, and root-cause analysis of semiconductor lasers, tunable laser sources, DFB lasers, external-cavity lasers, laser diodes, and semiconductor optical amplifiers.
Sr. Staff Engineer, Package and Interconnect Reliability Ayar LabsSr. Staff Engineer, Package and Interconnect ReliabilitySan Jose, CaliforniaYou will work closely with advanced foundry partners (including TSMC) to qualify advanced packaging technologies like COUPE (Compact Optical Engine), micro-bump/hybrid bonding, precision die attach, and critical optical-to-electrical interfaces such as Fiber Array Units (FAUs) and optical connectors. Failure Analysis & Physics of Failure (PoF) Root Cause Analysis: Drive deep-dive Failure Analysis (FA) on components that fail during reliability stress testing using advanced techniques (e.g., CSAM, High-resolution X-ray, SEM/EDX, FIB, and optical interferometry).
Senior Package Reliability Engineer Altera SemiconductorSenior Package Reliability EngineerSan Jose, CaliforniaWith more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. 8+ years of experience using thermal and thermomechanical simulation tools (e.g., Ansys, Abaqus, COMSOL, or equivalent) to develop and analyze warpage, coplanarity, stress, and deformation models for advanced semiconductor packages.
Senior Mechanical Engineer- Neck Rhoda AISenior Mechanical Engineer- NeckMountain View, CaliforniaYou'll own actuation selection and packaging for the neck's degrees of freedom, drive the head stabilization strategy with controls engineers, define the mass and CG budget the head team designs to, and coordinate the interfaces to torso, head, and cladding. Develop and validate the head stabilization strategy in collaboration with controls engineers — structural stiffness, backlash and compliance management, vibration isolation, and the dynamic performance needed for stable imagery from head-mounted cameras.
Lead Mechanical Engineer, Compute Systems Cowboy SpaceLead Mechanical Engineer, Compute SystemsSan Carlos, CaliforniaOur satellites operate in Low Earth Orbit to collect sunlight and enable a new class of capabilities—from powering on-orbit compute, to transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit compute to delivering secure, high-bandwidth optical data. Export Control Requirement: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicants must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.
Senior Mechanical Hardware Engineer - ECU Connectors & Interfaces General MotorsSenior Mechanical Hardware Engineer - ECU Connectors & InterfacesSunnyvale, CA$125,200–$192,700 / yearCoordinate closely with electrical engineers and PCB designers on connector pinout constraints, PCB attachment strategy, soldering or alternate mounting concepts, grounding paths, shielding interfaces, and packaging of high-speed and power connections into complete electromechanical systems. Own mechanical design of connector-related content from concept through production release, including connector housings, integrated or discrete headers, terminal retention features, bus bar interfaces, seals, gaskets, and attachment features to the ECU housing.