Independently troubleshoot elaboration failures, library mismatches, SDC constraints, FSDB parsing issues, multi-rail UPF problems, and power accuracy gaps across VCS, Verdi, PrimeTime, and RTL Architect. You are the engineer who can walk into a customer meeting, listen to their design constraints and flow pain points, then sketch out a deployment plan that accounts for their NDM import mess, their multi-rail UPF complexity, and the fact that their verification team has never heard of CGE.