You design, develop, and maintain scalable verification testbenches using SystemVerilog, UVM, and C++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven verification, and assertion-based techniques to validate complex block and subsystem behaviors. You ensure functional and performance excellence across subsystem coverage by help advancing verification methodologies, tools, and automation to improve efficiency and quality, while creating targeted and scalable test scenarios that stress interactions across multiple blocks, interfaces, and data paths within the subsystem.