Founding Design Engineer SiriusFounding Design EngineerSan Francisco, CaliforniaBacked by a16z Speedrun, we build AI agents that help consumer subscription brands — like Higgsfield and Promova — retain more users, extend lifetime value, and grow fast. We back each other on hard days, celebrate the great ones, and protect the time teammates need to be parents, partners, and humans first.
Mixed-Signal CMOS IC Design Engineer AttoTudeMixed-Signal CMOS IC Design EngineerMenlo Park, California$160,000–$250,000 / yearProven expertise in designing high-speed interconnects, Fractional-N synthesizers, PAM4 SerDes (>112Gbps), Equalizers, and multi-phase clock generation. Design and optimization of Fractional-N synthesizers, multi-phase clock generation, and analog building blocks (e.g., Charge Pumps, Power Control).
Senior Design Engineer Petra SecuritySenior Design EngineerSan Francisco, CaliforniaWhen Figma is too slow or too static for motion, interaction, keyboard behavior, AI workflows, or information-dense views, you build the real thing to find the answer. LLM-powered phishing messages get past email security, allowing attackers to compromise accounts and exfiltrate sensitive data in minutes.
Design Engineer III MindlanceDesign Engineer IIISunnyvale, CA$80–$87 / hourPerform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams. Day-to-day: build/run testbenches and regressions, analyze coverage, debug failures, and measure power/performance with the design team; work daily with 2 3 teammates and other CWs.
Circuit Design Engineer - New College Grad 2026 NvidiaCircuit Design Engineer - New College Grad 2026Santa Clara, CAMore recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA's invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.
Senior Photonic Layout Design Engineer NvidiaSenior Photonic Layout Design EngineerSanta Clara, CAAutomation & AI-Assisted Workflows: Develop and implement AI-assisted design methods, layout automation scripts, and custom Pcells to improve productivity, reduce development cycle times, and customize DRC/LVS checking flows. What You'll Be Doing: As a Senior Photonics Layout Engineer, you will take ownership of the physical design and verification of cutting-edge photonic integrated circuits (PICs), guiding designs from initial proof-of-concept phases to high-volume manufacturing readiness.
Senior Logic Design Engineer NvidiaSenior Logic Design EngineerSanta Clara, CAVerilog/System Verilog expertise required, with a deep understanding of ASIC/FPGA/CPLD development flow including RTL development, verification, logic synthesis, prototyping, DFT, timing analysis, and lab bring-up/debug. Cross-functional collaboration: Excel in cross-functional collaboration between firmware and hardware teams, which is crucial during design development, bring up and working through customer issues.
Asic Design Engineer - New College Grad 2026 NvidiaAsic Design Engineer - New College Grad 2026Santa Clara, CAThis position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
Senior Circuit Design Engineer NvidiaSenior Circuit Design EngineerSanta Clara, CAMore recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Product Design Engineer xponentiateProduct Design EngineerSan Francisco, CAThe position oversees command palette user experience, screen flows, accessibility features, and delivers frequent product previews. The role is hybrid with onsite collaboration in San Francisco, focused on fast-paced, iterative shipping of design improvements.
Senior Design Engineer, Coherent High Speed Interconnect NvidiaSenior Design Engineer, Coherent High Speed InterconnectSanta Clara, CAThe NVLINK-C2C enables the creation of a new class of integrated products with NVIDIA partners, built via chiplets, allowing NVIDIA GPUs, DPUs, and CPUs to be coherently interconnected with custom silicon. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
Package Design Engineer Broadcom CorporationPackage Design EngineerSan Jose, CARESPONSIBILITIES: Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. Job Description: Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.
Lead Asic Design Engineer Broadcom CorporationLead Asic Design EngineerSan Jose, CA$143,800–$230,000 / yearRTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs). Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
Physical IC Design Engineer Broadcom CorporationPhysical IC Design EngineerSan Jose, CA$143,800–$230,000 / yearThis position involves working with the latest technology to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Physical Design Engineer Broadcom CorporationPhysical Design EngineerSan Jose, CAThis position involves working with the latest technology to continue driving next generation AI/ML ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
Staff / Senior Staff Physical Design Engineer Bolt GraphicsStaff / Senior Staff Physical Design EngineerSunnyvale, CaliforniaBolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. Drive timing closure (setup/hold) across multiple PVT corners using advanced STA methodologies (OCV/POCV).
Design Engineer WorkOSDesign EngineerSan Francisco, CaliforniaRemoteAs AI reshapes software, WorkOS is at the frontier of Human and Agent Authentication, Identity, and Access Control helping companies answer a new critical question: who are your agents, and what are they allowed to do? You’ll help bring ambitious ideas to life by prototyping directly in code, validating with customers, and shipping production experiences with a high bar for craft.
Principal Photonics IC Design Engineer NvidiaPrincipal Photonics IC Design EngineerSanta Clara, CAWe are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning our photonics integrated circuit (PIC) product - from architecture definition through production tapeout and silicon validation. What We Need to See: PhD in Electrical Engineering, Physics, Applied Physics, or a closely related field with emphasis on integrated photonics, silicon photonics, or photonic device physics (or equivalent experience).
NewDesign Engineer HotplateDesign EngineerSan Francisco, CaliforniaYou'll upgrade the design of what we've already built, keep it consistent as the product grows, design and build the UI for entirely new parts of Hotplate as we ship them, and be a thought partner for most of the engineers on what the UI for their features should look like. We support the top pop ups in the country, many of which are recognized by the New York Times, Infatuation, Eater, etc. and recently crossed 5,000 businesses and $80M paid out on the platform, but we're just getting started.
Design Engineer III eTeam Inc.Design Engineer IIISunnyvale, CAPerform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams. About the role: Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement.