Support post-silicon bring-up of the Networking functionalityBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting Networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs Experience with SmartNIC/IPU/DPU architectures and their usages: Network virtualization, storage disaggregation, overlay networking, virtual switch, firewall/ACLs, and PSP gateways, including offload mechanisms Experience with datacenter Networking technologies and protocols such as Ethernet, IPv6, TCP/UDP, Geneve, PSP, and SRv6, including offload mechanisms for TCP segmentation, reassembly, checksum, and receive-side scaling Experience with RDMA and storage protocols and fabrics, including RoCEv2 and NVMe/NVMe-over-Fabric (TCP and RDMA) Experience with congestion control (e.g., DCQCN) and emerging transports such as UET and comparable next-generation RDMA transports Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms -- transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) -- and their impact on latency, fairness, bandwidth partitioning, and throughput Experience with datacenter network topologies and fabric architectures (e.g., Clos/fat-tree, rail-optimized fabrics) and their performance implications, including oversubscription, ECMP/load balancing, and end-to-end latency and congestion behavior Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., IPSec, PSP) Experience with domain-specific dataplane languages such as P4 Experience with data center workloads and their networking characteristics Experience with analytical performance-modeling methods (e.g., queueing theory, Little's Law, bandwidth-delay/outstanding-transaction sizing) Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience architecting networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs Experience designing high-performance offload architectures for NVMe-over-Fabric Experience designing data-plane offload/acceleration architectures using programmable processors/engines (programmable parsers, match-action, etc.) Experience designing high-performance inline data encryption engines, such as for IPSec and PSP Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience with GPU, machine learning, multi-threaded programming paradigm Experience with emerging RDMA transports such as UET and comparable next-generation RDMA protocols Experience with post-silicon performance validation and model-to-hardware correlation methodologies Experience with performance modeling and workload characterization for networking architectures, including analytical methods (e.g., queueing theory, Little's Law) and frameworks such as SystemC Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization Experience designing scheduling, arbitration, or rate-limiting/traffic-management hardware (e.g., hierarchical schedulers, WRR/DWRR/strict-priority arbiters, shapers/policers) Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysisMeta builds technologies that help people connect, find communities, and grow businesses. Architect the Networking datapath for our DPUs - packet processing and offloads, Network virtualization and overlays, RDMA and storage transports, and inline security - from early path-finding through silicon bring-up Decide what runs in the datapath engines, what runs in firmware, and what stays in host software, and design the interfaces between them Define how software programs and controls the datapath - match-action tables, rule and flow programming, register and descriptor interfaces, and the offload interfaces firmware and drivers build on Work closely with firmware, driver, and software teams so the datapath and its interfaces are clean, efficient, and genuinely usable, and evolve them as needs change Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints.