Principal DFT Engineer Silicon Engineering Space Exploration Technologies CorpPrincipal DFT Engineer Silicon EngineeringPalo Alto, CA$220,000–$355,000 / yearRESPONSIBILITIES: Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Staff/ Principal AI Engineer - Cortex Code Agentic System Snowflake IncStaff/ Principal AI Engineer - Cortex Code Agentic SystemMenlo Park, CA$236,000–$339,200 / yearAs a Staff/Principal AI Engineer on Cortex Code Quality, you will help define architect agent behavior at enterprise scale by building the agentic systems and methodology that make our users build cutting edge agentic systems that are efficient, repeatable, auditable, and shippable. Hill-climb infrastructure: Design and evolve pipelines and tooling that support large-scale experimentation, error mining, and iteration on prompts/tools/workflows with clear before/after signals.
Principal Product Engineer Microsoft CorpPrincipal Product EngineerMountain View, CA$142,800–$274,800 / yearRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. To achieve this goal, the Silicon Manufacturing & Packaging Engineering (SMPE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.
Principal Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpPrincipal Design Verification Engineer Silicon EngineeringSunnyvale, CA$210,000–$310,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Principal Data Engineer Analog DevicesPrincipal Data EngineerSan Jose, CaliforniaRequirements: Must have a Bachelor’s degree in Computer Science, Data Engineering, Information Systems, or related technical field (willing to accept foreign education equivalent) and five (5) years of experience leading large-scale data engineering, governance and MDM initiatives across multiple business domains. DE designing and delivering scalable cloud and on premises data platforms leveraging AWS, Redshift, Hadoop, and Hive, with experience building real time and batch data pipelines using distributed frameworks and big data technologies, and programming in Python, SQL, and PL/SQL.
Principal Engineer Quality Northrop Grumman CorpPrincipal Engineer QualitySunnyvale, CA$103,600–$155,400 / yearThe ideal candidate must be able to communicate written and verbally in a team environment, ability to use Microsoft Office Suite (Word, Projects, and Excel), and the ability to successfully engage with manufacturing and quality control personnel on the shop floor to provide solutions, coach, and mentor others in the use of Quality principles and practices. Basic Qualifications for the Principal Engineer Quality: Bachelor''s degree in a related STEM field with 5 or more years of experience in a quality assurance, mission assurance, or related engineering role; Master''s with 3 or more years of experience.
Principal Product Definition Engineer SemtechPrincipal Product Definition EngineerSan Jose, CaliforniaSemtech is a leading supplier of high-performance analog and mixed-signal semiconductors powering high-speed optical interconnects for hyperscale and AI data center networks, enterprise networking, wireless infrastructure, and passive optical access networks. The successful product definition engineer has deep technical credibility both inside and outside of Semtech, as well as good analytical and communication skills; and plays a critical leadership role as an interface between product marketing and engineering teams, defining technical requirements, performance targets, and features for our next-generation IC products.
Principal Group Software Engineering Manager Microsoft CorpPrincipal Group Software Engineering ManagerMountain View, CA$165,600–$296,400 / yearThere is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year. In July 2026, Microsoft introduced Project Perception, an agentic security system that brings together coordinated red, blue, and green AI agents to help organizations defend against cyber threats at machine speed.
Principal Power And Board Design Engineer Astera LabsPrincipal Power And Board Design EngineerSan Jose, CA$209,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Digital Design Engineer (AI Fabric) Astera LabsPrincipal Digital Design Engineer (AI Fabric)San Jose, CA$185,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Digital Design Engineer Astera LabsPrincipal Digital Design EngineerSan Jose, CA$185,000–$230,000 / yearYou'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principal Power and Board Design Engineer Astera LabsPrincipal Power and Board Design EngineerSan Jose, CA$209,000–$230,000 / yearWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable.
Principal Emulation Engineer Astera LabsPrincipal Emulation EngineerSan Jose, CA$209,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal RF Payload Lead Engineer SkyloPrincipal RF Payload Lead EngineerMountain View, CA$255,000–$270,000 / yearThe Principal RF Payload Lead owns the complete technical solution-from requirements definition and system architecture through hardware delivery, integration, testing, and mission operations support-of a space-qualified phased-array payload integrated with cellular networks and deployed at constellation scale. Our direct-to-device service is live on millions of activated devices across five continents, covering more than 72 million square kilometers, in partnership with leading satellite operators, mobile network operators, Tier-1 chipset makers, and OEMs worldwide.
Principal Physical Design Engineer, Methodology Astera LabsPrincipal Physical Design Engineer, MethodologySan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Physical Design Engineer, STA Astera LabsPrincipal Physical Design Engineer, STASan Jose, CAAs an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principal IP Signoff & Methodology Engineer Astera LabsPrincipal IP Signoff & Methodology EngineerSan Jose, CA$175,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Product Engineer Astera LabsPrincipal Product EngineerSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Digital RTL Engineer Astera LabsPrincipal Digital RTL EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. You'll own designs from specification through silicon bring-up, set the technical direction for complex AMS blocks, and mentor engineers across the team - turning ambitious architecture into production-proven products that ship at scale.
Principal Analog Mixed-Signal Design Engineer Astera LabsPrincipal Analog Mixed-Signal Design EngineerSan Jose, CA$207,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.