BS in Computer Science or related field with 10+ years of relevant industry experienceProficient in programming using Python, Perl or Tcl Hands-on experience with industry PNR and timing tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler, PrimeTime, or Tempus Experience taking block-level or chip-level designs through physical implementation and signoff closure on production silicon Experience in timing closure, signal integrity, low-power design techniques, and clock-tree construction Excellent communication skills and ability to collaborate across design, CAD, and technology teams Understanding of tradeoffs to meet PPA (power, performance, area) targets, and experience defining implementation recipes to improve PPA. The Physical Design Signoff Engineer will define and own the signoff criteria for PD/PNR designs across static timing analysis, signal integrity, EMIR, and clock construction and simulation, and will drive signoff reviews with design teams through readiness assessment, closure of open items, and alignment of methodology across groups.