ResponsibilitiesManage, mentor, and support the Software Engineering teamWork with Program Managers and Project Engineers to translate program requirements into engineering tasksProject scheduling and manpower estimatingWork with subject matter experts to develop detailed plans for new productsDevelop technical strategies to achieve Engineering goalsManpower planning for Software Engineering team across multiple projectsManage tools and infrastructure required for Software EngineersCommunicate Engineering team goals with staff membersDetermine training needs for the Software Engineering teamImplement and monitor performance metrics and give annual reviewsReview your team's work for technical accuracy and qualitySonatech software representative to customersProvide regular status updates on Engineering work to Project Managers (in the form of meetings, briefings, and/or technical reports)Provide technical input for proposals and business development activitiesHire and train new Software Engineering staffRequirementsBachelor's degree in Software Engineering or equivalent10+ years of experience developing software5+ years of engineering managementExperience with both Agile and Waterfall project managementExperience with CI/CD methodologyExperience developing in a CMMC Cyber Security environmentUnderstanding of Software Quality Assurance processesAnalytical skills for evaluating risks associated with product design, development, schedule, manufacturing, deployment, maintenance, etc. Strong organizational skills for tracking requirements, technical progress, staffing, and schedulesEffective leadership skillsStrong interpersonal and communication skills for overseeing staff, communicate instructions and expectations, and coordinating with other management personnelMust be a U.S. citizen with the ability to obtain a U.S. Secret Clearance; active or previous Security Clearance is desiredPreferred QualificationsSoC & CPU‑FPGA Co‑Design - Experience with system‑on‑chip architectures, especially designs that involve shared memory or tight CPU‑FPGA interaction.