Co-design tiling, scheduling, the instruction set architecture (ISA), the SRAM and High Bandwidth Memory (HBM) hierarchy, network-on-chip (NoC) traffic, and multi-chip mapping across pipeline, tensor, and sequence parallelism, including collectives. 8+ years of experience in hardware modeling, functional modeling, performance modeling, performance simulation, or accelerator performance analysis used by architects, RTL, compiler and runtime, or silicon teams.