Product Design Engineer II Pinnacle Technical ResourcesProduct Design Engineer IICupertino,, California$50–$60 / hourContractorThe specific compensation for this position will be determined by a number of factors, including the scope, complexity and location of the role as well as the cost of labor in the market; the skills, education, training, credentials and experience of the candidate; and other conditions of employment. Client’s approach to packaging is unique, so we value people who are eager to learn new skills and further improve their knowledge of packaging design, manufacturing processes, and sustainable materials.
Flexible Packaging Engineer - Destiny Packaging |Salinas, CA Bunzl plcFlexible Packaging Engineer - Destiny Packaging |Salinas, CASalinas, CAUnderstanding of the chemistry of poly urethane, poly vinyl, and poly olefin films, single direction and bi-directional shrink films, barrier and co extruded poly films is preferred. Experience with MAP, barrier films, laminated structures, COEX films, SUPs, flexo print, shrink, stretch, and poly bag structures is preferred.
Senior IC Packaging Engineer Axiado CorpSenior IC Packaging EngineerSan Jose, CAAxiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Companys 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliances 2025 Start-Up to Watch award. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management.
Senior Packaging Engineer Zp Group LlcSenior Packaging EngineerSaratoga, CA$210,000–$265,000 / yearKeywords: advanced packaging, flip‑chip, multi‑chip module, MCM, organic substrate, CoWoS, 2.5D, 3D packaging, TSMC system‑on‑wafer, OSAT, Wistron, module integration, cold plate integration, wafer‑level assembly, substrate technology, semiconductor packaging, high‑density interconnect, HDI substrates, yield improvement, semiconductor manufacturing, module engineering. The ideal Senior Packaging Engineer will lead advanced component and system‑level packaging efforts, with a strong emphasis on pcb assembly and organic substrate technologies on site in Saratoga, CA.
Packaging Engineer Nexthop Systems IncPackaging EngineerSanta Clara, CAQualification plans to characterize and validate packaging solutions for product and it's FRU (Field replaceable unit), subassemblies or components as per industry or internal specifications by working closely with HW design (mechanical, thermal, electrical etc.) Come out with innovative ideas for cost optimization, durability during shipping, environmental impact, and compliance with safety regulations. In this role, you'll combine technical expertise with innovative problem-solving to plan & execute all qualifications activities for cutting-edge packaging designs, ensuring they meet the stringent demands of all global shipping environments.
Photonic Packaging Engineer, Principal Astera Labs IncPhotonic Packaging Engineer, PrincipalSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
NewStaff IC Packaging Engineer - Advanced Packages & Power Analog DevicesStaff IC Packaging Engineer - Advanced Packages & PowerSan Jose, CAAnalog Devices, Inc. is searching for a highly motivated Staff Semi Packaging Engineer based in San Jose, CA. The position focuses on advanced IC package platforms, project management, and collaboration with cross-functional teams.
Advanced Packaging Engineer DensityAIAdvanced Packaging EngineerMountain View, CA$200,000–$350,000 / year10+ years of experience on very high performance designs at advanced packaging like SIP, CoWoS, EMIB and other interposer technologies. Demonstrated ability to work closely with architects to create right packaging solutions and sign off complex packaging solutions.
Flexible Packaging Engineer BunzlFlexible Packaging EngineerSalinas, CAFull timeUnderstanding of the chemistry of poly urethane, poly vinyl, and poly olefin films, single direction and bi-directional shrink films, barrier and co extruded poly films is preferred. Experience with MAP, barrier films, laminated structures, COEX films, SUPs, flexo print, shrink, stretch, and poly bag structures is preferred.
NewFlexible Packaging Engineer Destiny Packaging Inc.Flexible Packaging EngineerSalinas, CAPart timeUnderstanding of the chemistry of poly urethane, poly vinyl, and poly olefin films, single direction and bi-directional shrink films, barrier and co extruded poly films is preferred. Experience with MAP, barrier films, laminated structures, COEX films, SUPs, flexo print, shrink, stretch, and poly bag structures is preferred.
Memory Packaging Engineer Apple IncMemory Packaging EngineerSanta Clara, CAMinimum requirement of a bachelors degree in a relevant fieldMS or PhD preferred, with 3+ years of industry experience in package design and assembly process development of high-bandwidth and high-density memory packages. If you are driven to solve the industrys toughest packaging challenges, your work will have a profound and lasting impact on the products used by millions.
NewSenior IC Packaging Engineer - NPI & HVM Leadership Broadcom CorporationSenior IC Packaging Engineer - NPI & HVM LeadershipSan Jose, CAWith a strong educational background in engineering and extensive hands-on experience in advanced IC packaging, you will manage packaging deliverables, ensuring optimal design and execution throughout the lifecycle.#J-18808-Ljbffr. You'll collaborate closely with chip design, system design, and manufacturing teams to deliver industry-leading package solutions.
Sr Packaging Engineer Applied Materials IncSr Packaging EngineerSanta Clara, CA$133,500–$183,500 / yearIf you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members.
NewPackaging Engineer: IC & Power Module Design Analog DevicesPackaging Engineer: IC & Power Module DesignSan Jose, CA$86,480–$118,910 / yearA Bachelor's degree in Materials Science, Electrical Engineering, or related fields is required, along with knowledge in IC design, data analysis, and programming in Python. Analog Devices, Inc. seeks a Packaging Engineer in San Jose, CA, to design and optimize IC packages for diverse products.
NewPackaging Engineer Analog DevicesPackaging EngineerSan Jose, CA$86,480–$118,910 / yearPackage-level and system-level thermal/mechanical/electrical/magnetic simulation skill is a plus.*For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers.
Staff Semi Packaging Engineer Analog DevicesStaff Semi Packaging EngineerSan Jose, CaliforniaADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.
NewSenior Substrate & 3DIC Packaging Engineer TSMC - Taiwan Semiconductor Manufacturing Company LimitedSenior Substrate & 3DIC Packaging EngineerSan Jose, CAA leading semiconductor foundry in San Jose seeks a highly skilled Substrate / Advanced Package Engineer to innovate in 3DIC design and packaging. Responsibilities include designing, simulating, and optimizing advanced packaging technologies while collaborating with cross-functional teams.
Silicon Photonics & Optical Packaging Engineer Apple IncSilicon Photonics & Optical Packaging EngineerCAIn this highly visible role, you will develop Si photonics engine/chiplet packaging and co-packaging solutions utilizing advanced packaging technologies, define assembly baseline processes, decide package BOM, establish optical coupling design/manufacturing that are optimized for performance, reliability, yield and cost. Si photonics based optical engine package architecture / Package integration and drive micro-optical component assembly/interface characterization through Innovation Work with optical component vendors, foundry and OSAT to bring Si photonics packaging solution from concept to HVM.
Advanced Packaging Process Engineer Tenstorrent IncAdvanced Packaging Process EngineerSanta Clara, CAPartner with design, reliability, and architecture teams to evaluate tradeoffs (bump pitch, stack-ups, embedded Si, etc.) and lead test vehicle planning to meet program needs. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
NewMechanical Packaging Engineer Co-op NokiaMechanical Packaging Engineer Co-opSunnyvale, CAD. student in mechanical engineering, physics, or other similar fields or related field with an accredited school in US.RESPONSIBILITIESPerform mechanical integrity and thermal simulations, tolerance analyses and characterization. Solid interpersonal, communication and problem‑solving skills in order to interact with engineering staff, external vendors and contractors effectively.
Senior Engineer, Semi Packaging Engineering Analog DevicesSenior Engineer, Semi Packaging EngineeringSan Jose, CaliforniaRequirements: Must have a Master’s degree in Mechanical Engineering, Materials Science, Electrical Engineering, Autonomy and Robotics Engineering, or related field (willing to accept a foreign education equivalent) and two (2) years of experience as a Packaging Engineer or related occupation conceptualizing and productizing semiconductor devices to bridge analog signals to digital Cloud. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.
Integrated Circuit - Packaging Architect Engineer Advanced Micro Devices, IncIntegrated Circuit - Packaging Architect EngineerSan Jose, CaliforniaSuccessful candidate would collaborate with product design teams and technology development partners to understand future product needs and define a packaging roadmap that includes architecture, process definition, Design for Manufacturing (DFM) and Design for Yield (DFY) guidelines. Responsibilities: The Role : Advanced packaging technology leader driving packaging architecture across client, server, gaming and GPU products.
NewSenior Electrical Engineer / Product Lead Advanced Semiconductor Packaging and Integration Macpower Digital Assets Edge Private LimitedSenior Electrical Engineer / Product Lead Advanced Semiconductor Packaging and IntegrationSanta Clara, CA$64 / hourIf you enjoy solving complex challenges in mixed-signal design, chiplet integration, and high-performance electronics , this role is for you. We are looking for a Senior Electrical Engineer with deep expertise in semiconductor design, advanced packaging, and ASIC development .
Software Engineer 5 - Ads Pricing & Packaging Netflix IncSoftware Engineer 5 - Ads Pricing & PackagingLos Gatos, CA$388,000–$619,000 / yearThe Ads Pricing and Packaging team is responsible for developing cutting-edge inventory management systems which support various monetization strategies, including dynamic pricing, rate card management, product packaging, inventory segmentation, and yield optimization. Skills & experience we're seeking: Professional experience in building inventory management solutions that support monetization strategies such as dynamic pricing, rate card management, product packaging, inventory split and yield management.
Advanced Packaging Engineer - SI/PI Marvell Technology IncAdvanced Packaging Engineer - SI/PISanta Clara, CA$97,630–$146,300 / yearHighlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. Expected Base Pay Range (USD) $97,630 - $146,300 per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.
Packaging Assembly Engineer Apple IncPackaging Assembly EngineerCupertino, CAIn this highly visible role, you will own development, optimization and sustaining the advanced flip-chip BGA (FCBGA) assembly process from pathfinding, NPI through high-volume manufacturing by defining assembly baseline processes, deciding package BOM, establishing package design rules that are optimized for performance, reliability, yield and cost for a variety of projects including SoC. Define and optimize end-to-end FCBGA assembly process flow (wafer back-end interface, flip-chip attach, underfill, lid/heat spreader attach, ball attach, singulation, final inspection).
Sr. Principal Engineer, Advanced Packaging Marvell Technology IncSr. Principal Engineer, Advanced PackagingSanta Clara, CAThe group focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, high speed signaling and complex power delivery networks (PDNs) requiring innovative and custom solutions to meet constantly evolving customer needs. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Packaging Product Design Engineer Apple IncPackaging Product Design EngineerCupertino, CACollaborate with cross-functional teams including industrial design, hardware, environmental, operations, and technology groups to refine and execute on the design on the packaging. Apple's approach to packaging is unique, so we value people who are eager to learn new skills and further improve their knowledge of packaging design, manufacturing processes, and sustainable materials.
Co-Packaged Optics Packaging Process Development Engineer Marvell Technology IncCo-Packaged Optics Packaging Process Development EngineerSanta Clara, CAWork with cross-functional packaging teams and lead process development at foundry along with 2.5D/3D CoW process development with particular emphasis on chemistry development with packaging consumable suppliers at OSATs to bring packaging solutions from concept to prototypes and ramp to high volume manufacturing with aggressive cost reduction strategies. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Foundry Services Advanced Packaging Account Technical Solutions Engineer Intel CorpFoundry Services Advanced Packaging Account Technical Solutions EngineerSanta Clara, CA$220,320–$311,040 / yearBusiness group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
NewSenior Reliability Engineer - LPU Packaging NvidiaSenior Reliability Engineer - LPU PackagingSanta Clara, CACome join the team and see how you can make a lasting impact on the world!## **What you'll be doing:*** Own the package‑level reliability spec for assigned products* Define qualification requirements and pass/fail criteria for device/package‑level reliability (e.g., HTSL, TCT, UHAST, pre‑conditioning, JESD22 methods) and Package‑on‑board / board‑level reliability (thermal cycling, shock/vibration, connector/cage interactions)* Leads materials and stackup selection (substrate, solder alloy, underfill, mold, lid, TIM, etc.) and DFR trade‑offs for new packages and 2nd sources* Evaluates thermo‑mechanical and SI/PI impact of those choices* Analyzes qual and stress data (including HTOL, package qual, SLT/system stress) and convert to design / process/ material changes for next revision.* Senior Reliability Engineer - LPU Packaging page is loaded## Senior Reliability Engineer - LPU Packaginglocations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2013787NVIDIA is looking for a Senior Reliability Engineer to join our LPU packaging team.
Advanced Packaging Technologist Google LLCAdvanced Packaging TechnologistSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. As an advanced packaging technologist, you will develop advanced packaging solutions (2.5D/3D/3.5D) for ML chips, which involves collaborating with architects, Signal Integrity (SI)/Power Integrity (PI), thermal, and Printed Circuit Board (PCB) engineers to create high-performance packages optimized for electrical performance, reliability, and assembly.
Semiconductor Packaging Modeling and Simulation Engineer onsemiSemiconductor Packaging Modeling and Simulation EngineerSan Jose, CAWith a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. As a semiconductor packaging modeling and simulation engineer, you will have the opportunities to support new power module development and new product design, assembly and process, quality and reliability, and customers in worldwide.
NewSenior Signal Integrity Engineer - 2.5D/3D Packaging Lead NVIDIA GruppeSenior Signal Integrity Engineer - 2.5D/3D Packaging LeadSanta Clara, CA$168,000–$264,500 / yearNVIDIA Gruppe is seeking a Senior Signal Integrity Engineer for its Packaging and Systems team in Santa Clara, California. The ideal candidate will lead high-speed SerDes channel design and signal integrity analysis.
NewSenior Signal Integrity Engineer - LPU Packaging NVIDIA GruppeSenior Signal Integrity Engineer - LPU PackagingSanta Clara, CA$168,000–$264,500 / yearWhat we need to see BS, MS, or PhD in Electrical Engineering or equivalent experience.8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles. Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, focusing on channel loss, discontinuities, return path behavior, and crosstalk.
Packaging Product Design Engineering Manager Apple IncPackaging Product Design Engineering ManagerCupertino, CAApple's approach to packaging is unique, so we value people who are eager to learn new skills and further improve their knowledge of packaging design, manufacturing processes, and sustainable materials. As a Packaging PD Manager, you will lead a team of engineers to design and execute packaging architecture from initial prototypes to mass production with sustainable packaging material.
Cloud Hardware Development, Packaging, Network Product Development - Optics Amazon.com IncCloud Hardware Development, Packaging, Network Product Development - OpticsCupertino, CAYou will perform high-quality design, development, validation, and sustaining engineering of IC and SOC packages for high-speed applications, working closely with design teams, manufacturing partners, and cross-functional stakeholders to deliver robust solutions at scale. Within AWS Networking the NPD (Network Product Development) organization is responsible for, designing the hardware, building the software, and owning the interconnects for the routers that power the global AWS network.
NewSenior Structural, Thermal & Packaging Engineer Applied MaterialsSenior Structural, Thermal & Packaging EngineerSanta Clara, CA$161,000–$221,000 / yearThe ideal candidate will possess a strong background in physics and demonstrated problem-solving abilities.#J-18808-Ljbffr. This full-time role involves defining experiments, troubleshooting complex systems, and mentoring less experienced colleagues.
Packaging Design Engineer GooglePackaging Design EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Utilize advanced Three-Dimensional/Two-Dimensional Computer-Aided Design software (SolidWorks, Artios CAD, Creo, etc.) to architect complex structural packaging solutions and generate precise technical drawings, assembly instructions, and cushion layouts.
NewEvening Packaging Test Engineer (Swing Shift) Ryzen SolutionsEvening Packaging Test Engineer (Swing Shift)San Jose, CAThis hands-on role involves analyzing data and ensuring project accuracy and quality through effective communication and documentation. The ideal candidate will hold a B.S. degree in a relevant field and have 2-5 years of laboratory experience.
Lab Packaging Test Engineer I Engineer In Training (Swing Shift) Artech LLCLab Packaging Test Engineer I Engineer In Training (Swing Shift)San Jose, CA$66,560–$70,720 / yearPerform testing duties within the designated workday hours according to requirements to ensure customer objectives are met through proactive communication, documentation, and customer service. Maintain responsive customer communication in email and in person regarding testing services provided, test status, updates, and results.
NewRemote Field Service Engineer - Semiconductor Packaging PacTech Packaging Technologies GmbHRemote Field Service Engineer - Semiconductor PackagingSanta Clara, CARemoteThe role involves providing exceptional onsite customer service, performing installations and maintenance on sophisticated semiconductor packaging equipment. PacTech Packaging Technologies GmbH is seeking a Field Service Engineer to join our dynamic team.
NewAdvanced Packaging Process Engineer III E3) Applied MaterialsAdvanced Packaging Process Engineer III E3)Santa Clara, CA$124,000–$171,000 / yearYour duties will include collecting and analyzing data, performing hardware characterization, troubleshooting engineering issues, measuring film properties, generating technical documentation, and engaging with customers to resolve concerns. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state‑of‑the‑art research and development projects.
NewAdvanced Packaging Integration Engineer (3D/Hybrid Bonding) Applied MaterialsAdvanced Packaging Integration Engineer (3D/Hybrid Bonding)Santa Clara, CA$138,000–$190,000 / yearA leading technology company in Santa Clara is looking for an Advanced Packaging Integration Engineer to develop high-performance optical interconnects. The position offers a competitive salary range of $138,000 to $190,000, along with a full-time role and opportunities for personal and professional growth.#J-18808-Ljbffr.
NewProcess Engineer II: Advanced Packaging & Lithography Applied MaterialsProcess Engineer II: Advanced Packaging & LithographySanta Clara, CA$100,000–$136,500 / yearThe successful candidate will be responsible for developing and optimizing manufacturing processes for semiconductor advanced packaging technologies, including hands-on experimentation and data analysis. Candidates will need hands-on experience in semiconductor packaging, particularly in lithography.#J-18808-Ljbffr.
Senior Power Integrity Engineer - LPU Packaging NVIDIA CorpSenior Power Integrity Engineer - LPU PackagingSanta Clara, CA$196,000–$310,500 / yearWe have some of the most forward-thinking and hardworking people in the world working with us and our product lines are growing fast in some of the hottest state-of-the-art fields such as Artificial Intelligence, Deep Learning, Autonomous Vehicles, and Robotics. A deep understanding of board-level PDN design, including stack-up definition, plane partitioning, and VRM placement on high-layer-count accelerator boards.
Senior Signal Integrity Engineer - LPU Packaging NVIDIA CorpSenior Signal Integrity Engineer - LPU PackagingSanta Clara, CADevelop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with strong focus on channel loss, discontinuities, return path behavior, and crosstalk. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast.
NewPrincipal IC Packaging & FEA Engineer LumilensPrincipal IC Packaging & FEA EngineerSan Jose, CAThe ideal candidate will possess a Bachelor's in Mechanical Engineering or related field and have extensive experience with FEA tools and advanced packaging technologies. A technology startup in San Jose is seeking an experienced IC Package Mechanical FEA Engineer to develop high-performance packaging solutions for advanced ASICs.
Manufacturing Design Engineer (MDE) - Packaging Apple IncManufacturing Design Engineer (MDE) - PackagingCupertino, CADevelop innovative solutions that enable Apple's Product and Environmental goals, including but not limited to manufacturability of fiber-based designs, lowering Apple's environmental footprint, and developing world class manufacturing solutions. (domestic and international up to 30%) A team player who is self-motived, defining and closing all engineering tasks to meet project objective, detailed oriented to cut to the root of problems, and ability to learn quickly with limited information or support.
NewSenior Process Integration Engineer - Advanced Packaging Applied MaterialsSenior Process Integration Engineer - Advanced PackagingSanta Clara, CAThe ideal candidate should have at least 10 years of experience, leading projects across various teams and showing strong communication skills. Applied Materials in Santa Clara, CA is looking for an expert in semiconductor packaging development.