General Summary: The engineer will be a key member of the Process Package Integration and bumping process team, driving technology development and new product introduction (NPI) with primary ownership of wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness across multiple silicon technology nodes, foundries, bumping lines, and assembly houses (OSATs). The role works closely with foundry FBEOL teams, bumping/assembly partners, and internal package design, process, quality, test, and product development teams to deliver robust bumping solutions enabling advanced packaging (flip-chip, RDL/fan-out, and 2.5D/3DIC).