PREferred SKILLS AND EXPERIENCE: • Master's degree or PhD in electrical engineering, computer engineering with emphasis in electromagnetic theory, transmission line theory, wireline transceivers, or power integrity • 5+ years of electronic product experience designing hardware from concept through production; strong emphasis on full life-cycle development of new hardware products and not small incremental updates to legacy hardware • 5+ years of experience architecting, implementing, and debugging cutting edge DSP based SERDES products (i.e. 56Gbps, 112Gbps, 224Gbps) working across package and PCB • 5+ years of experience specifying, analyzing, debugging, and working with high speed, high bandwidth memory interfaces • 5+ years of experience designing, implementing, and debugging power delivery networks for large processors, FPGAs, SoC, or ASICs with complex power requirements • Thorough understanding of wireline transceiver concepts, architectures, and circuits • Strong understanding of computers and programming languages (Python, C/C++) • Demonstrated ability to work in a highly cross-functional role • Experience with low loss laminates, high volume PCB manufacturing, and high-speed connectors • Experience debugging and resolving EMI/EMC de-sense problems • Passion for working in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit to deliver best in class products. 10 to 112+ Gbps) SERDES, DSPs, retimers, and optoelectronics • High-speed and high-bandwidth memory interfaces (DDR4, LPDDR5, GPDDR6, QSPI NOR, eMMC, etc.) • Power needs and PDNs for the associated ASICs • Work alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies • Derive top level specifications for PCB materials and channel subcomponents • Design and optimize transition structures for the entire channel from die bump to die bump • Drive detailed component selection to accompany your PDN designs • Root cause and fix issues found in PCB manufacturing, PCBA test, or satellite integration • Define best practices, simulation workflows, test methodologies, signoff criteria, and lab equipment needs for all SI/PI needs on Starlink satellite payloads.