The team is responsible for the architecture, design, and verification of a broad range of embedded microprocessor (MP) subsystems and hardware accelerators that are critical to enhancing performance, functionality, security, and efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms. Analyze regression failures, debug simulations, evaluate coverage results, and collaborate with design, verification, and implementation teams to achieve functional and design-quality closure, including lint, timing, DFT, DFP, and other signoff requirements.