Bachelors Degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline SerDes circuit design experience -OR- Master's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline SerDes circuit design, -OR- Ph. Define SerDes link architecture for next-generation interfaces (224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, UCIe): channel analysis, link budget, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.