Chip-Scale Design: digital, RF and/or mixed signal device packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip interconnect (chiplet, flipchip, wire/ribbon bonding), modeling & simulation (power, speed, timing, signal integrity, thermal, structural, reliability). The research team includes research scientists at multiple levels, ranging from Junior to Principal depending upon education and experience: Level 1 - No Degree with 6+ years of experience; Bachelor’s degree with 2+ years of related experience; Master’s degree with 1+ years of related experience.