Asic Physical Design Engineer, Netlisting - New College Grad 2026 NvidiaAsic Physical Design Engineer, Netlisting - New College Grad 2026Santa Clara, CAWhat you'll be doing: Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.
Post-Silicon Validation and Methodology Engineer NVIDIA CorpPost-Silicon Validation and Methodology EngineerSanta Clara, CAWays to stand out from the crowd: Hardware proof of crafting: debug infrastructure you built in the lab, characterization methodologies adopted across programs, build DFT feature specs or in-system test suites you developed, or margin test flows that caught issues before production. Proficiency in the use of AI tools to accelerate silicon validation work - automated analysis of bring-up logs, regression data, or lab instrumentation output; anomaly detection on silicon measurement datasets; or LLM-assisted debug triage.
NewHigh-Speed System Design Engineer (Multiple Positions) POINT2 TECHNOLOGY INCHigh-Speed System Design Engineer (Multiple Positions)San Jose, CAStrong familiarity with the operating principles of RF blocks (Mixers, Amplifiers), Analog Front-Ends (CTLE, VGA), and Digital Equalization techniques (FFE, DFE, MLSE). Develop comprehensive end-to-end system models in MATLAB/Simulink to simulate link performance, accounting for noise, non-linearity, and frequency-dependent losses.
NewSenior SRAM Engineer NVIDIA CorpSenior SRAM EngineerSanta Clara, CABe it high speed, low power, multiport, we engage closely with processor architecture teams to build custom solutions across the entire NVIDIA silicon portfolio. Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon.
Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity MarvellSenior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power IntegritySanta Clara, CaliforniaYou will own layout guideline definition, post-silicon channel extraction and simulation, compliance testing, and SerDes tuning guidance, while also reviewing customer PDN designs and feeding learnings back to Marvell's silicon and hardware engineering teams as part of a continuous improvement loop. Note on experience level: While the years of experience above represent the typical bar for this role, exceptionally talented candidates with fewer years but demonstrated mastery — through impactful project work, deep technical contributions, or industry recognition — are strongly encouraged to apply.
Analog Design Engineer Omnivision TechnologiesAnalog Design EngineerSanta Clara, CA$156,853–$160,000 / yearJob Title: Analog Design Engineer Job Duties:Conduct design and development of image sensor technologies, work on transistor level design of analog and mixed-signal circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp generator, ASRAM and XDEC by using Cadence Virtuoso. Design the internal Discrete-time Circuits, Peripheral circuits and Timing control for a CMOS image sensor, including bias circuits, driver/level shifter, switched capacitor, logic gates and slew rate control.
Staff Modeling and Simulation Engineer Commonwealth Fusion SystemsStaff Modeling and Simulation EngineerMilpitas, CARun Multi-Physics Analysis: Build, run, and evaluate highly coupled simulations covering structural mechanics, high-temperature thermal management, fluid/gas flow dynamics, and chemical reaction kinetics. Collaborate & Interface: Partner closely with cross-functional teams, including Mechanical Designers, Electrical Engineers, Materials Scientists, and Chemical Specialists, to translate simulation insights into actionable hardware modifications.
Applied AI Engineer - Vlsi Design NvidiaApplied AI Engineer - Vlsi DesignSanta Clara, CAThe successful candidate will work closely with our team of experts in VLSI design, machine learning, and software engineering to create and integrate machine learning-based solutions that enhance the efficiency, productivity, and quality of our VLSI design flows. We are looking for dedicated Software Engineers to work on developing and deploying AI agents that leverage machine learning models to solve complex problems in VLSI design.
Senior Electrical Engineer TerranovaSenior Electrical EngineerBerkeley, CaliforniaBacked by leading climate and American dynamism investors, Terranova builds intelligent robotic systems to terraform the Earth itself - lifting land, restoring wetlands, and protecting critical infrastructure from floods and sea-level rise. You’ll lead projects from concept through field deployment: designing, analyzing, fabricating, and testing large-scale robotic systems that operate in the most demanding environments on Earth.
Distinguished Engineer, Storage - AI Cloud NvidiaDistinguished Engineer, Storage - AI CloudSanta Clara, CAWhat you'll be doing: Lead the multi-year technical plan for AI Cloud Storage expansion across NCPs - determine the reference architecture, capabilities, performance and durability SLOs, qualification methodology, and roadmap for the high-performance file, object, and block storage that each NCP must offer to qualify for NVIDIA GPU allocation. Design the storage layer for workloads spanning the next several GPU generations, including disaggregated inference with storage-backed KV caching, large-scale write-once-read-many inference patterns, exabyte regional object stores, and cross-DC dataset versioning and copy management.
Senior Verification Engineer NvidiaSenior Verification EngineerSanta Clara, CAStrong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, with a passion for root-causing complex issues; experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches - ideally on shipped silicon. Domain knowledge of display pipelines: protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low-power features (clock gating, power domains, retention, entry/exit sequences).
Lead Mechanical Engineer, Compute Systems Cowboy SpaceLead Mechanical Engineer, Compute SystemsSan Carlos, California$150,000–$225,000 / yearOur satellites operate in Low Earth Orbit to collect sunlight and enable a new class of capabilities—from powering on-orbit compute, to transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit compute to delivering secure, high-bandwidth optical data. Export Control Requirement: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicants must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.
Electrical Engineer - Direct Hire PEAK Technical StaffingElectrical Engineer - Direct HireMilpitas, CAAssist project managers with all aspects of projects from proposal to final engineered design, ensuring high-quality outcomes and client satisfaction. Candidate Privacy To read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to https://peaktechnical.com/privacy-policy/and https://peaktechnical.com/ca-residents-privacy-rights/
NewEngineer II RosendinEngineer IIConcord, CaliforniaRequires working electrical engineering knowledge, including power distribution, lighting, grounding, energy conservation, and value engineering related to designing state-of-the-art constructible projects. Knowledge of various electrical engineering concepts, including power distribution, lighting, grounding, energy conservation, and value engineering related to designing state-of-the-art, constructible projects.
DFT Engineer, Google Cloud GoogleDFT Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly complex digital or mixed-signal chips or IPs.
Control Systems Networking Engineer GoogleControl Systems Networking EngineerSunnyvale, CAAs a Control Systems Networking Engineer, you will take on complex Operational Technology (OT) networking and infrastructure challenges to develop new technologies, and optimize processes to further increase our networking posture and networking infrastructure across products. To support delivering AI and Infrastructure at an unparalleled scale, efficiency, reliability and velocity, the Data Center Control Engineering team takes the control/networking design of our data centers into the future.
Principal Mechanical Engineer - Vacuum Commonwealth Fusion SystemsPrincipal Mechanical Engineer - VacuumMilpitas, CADedication to safety to mitigate industrial hazards that may include heat, cold, noise, fumes, strong magnets, lead (Pb), high voltage, high current, pressure systems, and cryogenics. Lead Design Reviews: Conduct rigorous reviews for overall mechanical systems and sub-systems, emphasizing manufacturability (DFx) and best practices for mechanical design.
Principal Analog/Mixed-Signal ASIC Engineer TaaraPrincipal Analog/Mixed-Signal ASIC EngineerSunnyvale, CaliforniaThe role requires extensive experience in ASIC design and layout—including top-level ownership of ASIC tape-outs at leading commercial foundries—and deep expertise in either or both of these two categories: high-precision AMS circuits and high-speed wireline/silicon photonics interface circuits. High-speed designs: Front-end circuits for optical communication, including modulator drivers and transimpedance amplifiers (TIAs) operating at tens of GHz, and broadband circuits for serial links including receivers, transmitters, and equalizers.
SCADA Engineer Adapture RenewablesSCADA EngineerOakland, CaliforniaDrawing upon an extensive knowledge base, we develop, finance, engineer, build, own, and operate high quality utility-scale photovoltaic projects and battery energy storage projects. This position will work in our Technology team to provide design, proactive, and reactive support services for our EPC and Asset Management teams.
Senior Commissioning Operations Engineer Mainspring EnergySenior Commissioning Operations EngineerMenlo Park, CaliforniaRemoteAt Mainspring, we are committed to building a diverse, inclusive, flexible, and collaborative environment, so if you want to help us transition the world to clean and affordable electricity, and don’t meet all posted requirements for a particular role, we’d still love to hear from you. The company began commercial shipments of its Mainspring Linear Generators in 2020 and today has hundreds of megawatts in advanced development and field operations for leading Fortune 500 companies, data centers, and utilities.