Key Responsibilities: Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs Implement designs using HDL (VHDL, Verilog, and/or SystemVerilog) Develop verification methodologies and test benches for block and system-level verification Create and execute test plans, develop test harnesses, and implement coverage models Conduct timing analysis, noise analysis, and other signoff checks Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering Support lab integration and troubleshooting activities Resolve design issues and drive solutions for timing, congestion, and other implementation challenges. Knowledge of DSP and communications systems including spread spectrum, forward error correction, and modulation types (QPSK, QAM, PCM/FM, PAM) Strong object-oriented programming and scripting skills (Python, TCL, Perl).