Strong hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout through logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, and ECOs. Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk.