Hands‑on experience with GPU shader core or shader subsystem microarchitecture, including:Instruction fetch, decode, dispatch, issue, and retirementScoreboard and dependency trackingRegister file design and banking optimizationOperand collection and bypass networksALU, FPU, SFU, tensor, or matrix execution integrationLoad/store unit and memory coalescingTexture, cache, and memory subsystem interactionBarrier, synchronization, atomic, and memory ordering logicContext switching, preemption, virtualization, or security supportPerformance counters, debug hooks, and hardware profiling supportClock gating, power gating, DVFS, and low‑power shader designExperience with modern GPU graphics and compute workloads, including vertex, pixel/fragment, compute, mesh, geometry, tessellation, ray tracing, or AI/ML shader workloads. Role and ResponsibilitiesDefine, develop, and own GPU shader system microarchitecture specifications for industry‑leading graphics and compute IP.Lead RTL design and microarchitecture development for shader‑related blocks, including shader core pipelines, thread dispatch, warp/wavefront scheduling, instruction issue, operand collection, register file access, scoreboard, dependency tracking, execution control, and pipeline flow control.