Position may require some international travel (10%).Drive volume stress testing and system-level validation of wireless chipsets (internal and vendor-supplied) using production firmware across multiple hardware configurations Debug and root-cause hardware and silicon failures on complex wireless silicon platforms involving multi-core CPUs, firmware, and inter-processor communication Capture and analyze analog and digital signals using oscilloscopes, logic analyzers, and protocol analyzers to isolate failures at the board, package, and silicon level Collaborate with firmware, software, and design teams to triage issues, reproduce field failures, and drive corrective actions through to resolutionBS and a minimum of 10 years relevant industry experience Solid understanding of SoC/PMU design and micro-architecture, with hands-on experience in silicon bring-up or post-silicon validation Experience with high-speed memory systems and digital communication interfaces (e.g., PCIe, RFFE, SPMI, DDR, USB, SPI, I2C) Familiarity with interpreting and navigating complex schematics and PCB layouts Working knowledge of hardware/software co-debug methodologies on multi-processor embedded systems Hands-on hardware debugging expertise, including the use of modern lab equipment (DSOs, logic analyzers, protocol analyzers), with prior experience in PCIe PHY validation being highly advantageousBS in Electrical Engineering, Computer Engineering with at least 4 years of relevant industry experience Proficiency in developing targeted tests to exercise specific aspects of silicon designs and digital interfaces Good understanding of modern operating systems, firmware, and device drivers, with the ability to create basic software routines and test scripts (e.g., Lua, Python, C) Experience with volume stress testing, reliability screening, or production-level validation of wireless or cellular modem chipsets Strong communication skills coupled with a proactive attitude for effectively presenting technical findings and driving hardware issues to closure in a cross-functional team environment. The digital hardware design engineer will closely work with internal hardware and silicon teams to bring-up, characterize (performance/power) and validate new digital interfaces + protocols.