NewProduct Quality Engineer (CAPA) - Only On W2 Kyyba IncProduct Quality Engineer (CAPA) - Only On W2Alameda, CA$35–$40 / hourContractorSupport Quality Systems (perform audits, SOP improvement, training, CAPA investigations). Support production efforts and process improvements (trend analysis, process validation, SPC).
Validation Engineer, KYYBA, IncValidation Engineer,San Francisco, CACollaborate across mechanical, electrical, system architecture, firmware development, and firmware validation teams to understand new component level hardware/software changes being developed and identifying test plans to validate the changes. ·Develop and execute firmware and hardware integration test plans on new hardware components and firmware features.
Senior RF Validation Engineer TacitSenior RF Validation EngineerSan Francisco, CaliforniaAutomate RF measurements across lab and production test setups using calibrated RF instrumentation and test systems, including VNAs, spectrum analyzers, real-time spectrum analyzers, signal generators, power meters, oscilloscopes, probers, power supplies, phase-noise or noise-figure measurement equipment, switch matrices, call boxes, wireless connectivity testers, and similar tools as needed. Perform systematic RF debug and root-cause analysis for impairments including Conduct coexistence (CoEx), leakage, blockers, desense, nonlinearities, compression, spurs, harmonics, reciprocal mixing, noise coupling, and related RF/system-level behaviors.
Hardware & Silicon Validation Principal Engineer MarvellHardware & Silicon Validation Principal EngineerSanta Clara, CAThe group validates complex, high performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing. The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators.
Principal Serdes Bring-Up Validation Engineer Astera LabsPrincipal Serdes Bring-Up Validation EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization), with the ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.
NewHardware Validation Engineer Pure Storage Inc.Hardware Validation EngineerSanta Clara, CAClassification of protected categories is as follows: A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability. Partner Cross-Functionally for Deployment Success: Collaborate directly with internal Hardware, firmware, software, test development teams and external customer and partner teams to resolve technical roadblocks and continuously elevate platform performance.
Senior Systems Validation Engineer NXP Semiconductor, Inc.Senior Systems Validation EngineerSan Jose, CA$130,600–$179,600 / year5-10 years of experience in systems validation with high-speed networking SerDes, mixed signal/analog/digital ICs and blocks, knowledge of PCS and PMA networking layers. Main Job Tasks and Responsibilities: System Validation planning- Develop and implement detailed validation test-plan covering all hardware and firmware configurations and develop validation methodologies/infrastructure to achieve the coverage.
Hardware & Wireless Validation Engineer Artech LLCHardware & Wireless Validation EngineerFoster City, CA$70–$88.55 / hourHands-on experience configuring/programming, developing test cases using wireless test platforms (Keysight, Rohde & Schwarz) and testing/troubleshooting Automotive Ethernet products. In this role, you will be responsible for developing, documenting, and executing comprehensive unit and system-level validation tests for both general hardware and network-connected devices.
Sensor System Validation Engineer Manpower EngineeringSensor System Validation EngineerFoster City, CA$70–$75 / hourTemporaryManpowerGroup® (NYSE: MAN), the leading global workforce solutions company, helps organizations transform in a fast-changing world of work by sourcing, assessing, developing, and managing the talent that enables them to win. We are recognized consistently for our diversity - as a best place to work for Women, Inclusion, Equality and Disability and in 2023 ManpowerGroup was named one of the World's Most Ethical Companies for the 14th year - all confirming our position as the brand of choice for in-demand talent.
Firmware Validation Engineer Artech LLCFirmware Validation EngineerFoster City, CA$75–$88.59 / hourResponsibilities include managing system specifications, conducting failure mode and effects analysis, creating and executing validation plans, overseeing firmware release schedules, managing supplier relationships, and maintaining detailed project development timelines. As a member of the chassis actuator engineering team at ***, you'll work to meet engineering milestones and collaborate with tier-one suppliers to validate and release control firmware for our brake system.
Hardware & Wireless Validation Engineer ICONMA, LLCHardware & Wireless Validation EngineerFoster City, CA$87.68–$89.88 / hourHands-on experience configuring/programming, developing test cases using wireless test platforms (Keysight, Rohde & Schwarz) and testing/troubleshooting Automotive Ethernet products. You will also perform or commission conformance testing for international regulatory requirements, such as FCC emission compliance, PTCRB/GCF test suites, and U.S. MNO conformance testing.
Hardware & Wireless Validation Engineer Ursus, Inc.Hardware & Wireless Validation EngineerFoster City, CA$78–$88.59 / hourTechnical Expertise: Hands-on experience configuring/programming, developing test cases using wireless test platforms (Keysight, Rohde & Schwarz) and testing/troubleshooting automotive Ethernet products. Experience using lab/RF equipment (oscilloscopes, spectrum analyzers, VNAs) and wireless test platforms (Keysight, Rohde & Schwarz), plus protocol/log analysis tools like Wireshark and QXDM.
Hardware & Silicon Validation Senior Staff Engineer MarvellHardware & Silicon Validation Senior Staff EngineerSanta Clara, CAThe group validates complex, high performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing. The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators.
PCIe Silicon Validation & Debug Engineer Pyramid Consulting, IncPCIe Silicon Validation & Debug EngineerSunnyvale, CARemote$43–$47 / hourPCIe Engineer" OR "PCI Express Engineer" OR "Silicon Validation Engineer" OR "Validation Engineer" OR "Post Silicon Validation Engineer" OR "Pre Silicon Validation Engineer" OR "Silicon Debug Engineer") AND (PCIe OR "PCI Express") AND (Validation OR Verification OR Debug OR "Silicon Bring-up") AND (SystemVerilog OR UVM OR Python). Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality.
Optical Validation Engineer, Principal Astera LabsOptical Validation Engineer, PrincipalSan Jose, CA$160,000–$200,000 / yearWe are seeking an experienced Optical (EIC/PIC) Validation Engineer at the Principal level to lead the validation, characterization, and qualification of advanced photonic integrated circuits (PICs) closely integrated with electronic integrated circuits (EICs) multiple optical configurations. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principal Silicon Validation Engineer, Serdes/Pam4 Astera LabsPrincipal Silicon Validation Engineer, Serdes/Pam4San Jose, CA$185,000–$240,000 / yearIn this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
High-Speed SERDES Validation Engineer Advanced Micro Devices, IncHigh-Speed SERDES Validation EngineerSan Jose, CaliforniaWorking closely with design, product, and test teams, you will translate pre-silicon models into real-world performance, develop scalable test methodologies, and drive improvements in product quality and manufacturability. Responsibilities: THE ROLE: AMD is seeking a High-Speed SERDES Validation Engineer to join a highly collaborative silicon engineering team driving cutting-edge connectivity for next-generation products.
Sensor System Validation Engineer Artech LLCSensor System Validation EngineerFoster City, CA$65–$78.35 / hourWork with systems engineers, software engineers, and sensor hardware engineers to create and iterate V&V methodologies for next-generation sensor architecture. D. degree in relevant fields OR a master's degree in engineering with 3 years of work experience in sensor/perception systems development and/or testing.
Senior HPC Systems Validation Engineer LambdaSenior HPC Systems Validation EngineerSan Jose, CaliforniaOur investors notably include TWG Global, US Innovative Technology Fund (USIT), Andra Capital, SGW, Andrej Karpathy, ARK Invest, Fincadia Advisors, G Squared, In-Q-Tel (IQT), KHK & Partners, NVIDIA, Pegatron, Supermicro, Wistron, Wiwynn, Gradient Ventures, Mercato Partners, SVB, 1517, and Crescent Cove. Our scope spans the full hardware lifecycle: roadmap and architecture, proof-of-concept for state-of-the-art platforms, new product introduction (NPI), and fleet-scale operations — all engineered for gigawatt-scale AI factories with rack-first design, advanced liquid cooling, and next-generation interconnects at the cutting edge of the industry.
PCIe Silicon Validation & Debug Engineer Pyramid, IncPCIe Silicon Validation & Debug EngineerSunnyvale, CA$43–$47 / hourFull timePCIe Engineer" OR "PCI Express Engineer" OR "Silicon Validation Engineer" OR "Validation Engineer" OR "Post Silicon Validation Engineer" OR "Pre Silicon Validation Engineer" OR "Silicon Debug Engineer") AND (PCIe OR "PCI Express") AND (Validation OR Verification OR Debug OR "Silicon Bring-up") AND (SystemVerilog OR UVM OR Python). Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality.