Lead physical implementation, from floorplanning through tapeout, including physically-aware, ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR, at all levels of the SoC hierarchy Define physical design methodology and flows to realize power and timing intent, and in doing so, meet milliwatt-level always-on power budgets in a wearable form factor, where thermal limits demand perf/mW compute efficiency Identify and resolve physical implementation bottlenecks related to congestion, timing, and power; then develop automation and AI-assisted flows to improve throughput and QoR Collaborate with RTL designers to provide implementation feedback that shapes the microarchitecture towards power- and area-efficient timing closure Work closely with package engineers to ensure the floorplan, clock tree, and power plan meet the product-level power delivery, signal integrity, thermal, and routability requirements Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness and meets debug and testability requirements Drive EDA vendor engagement, tool evaluations, and flow improvementsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Bachelor's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of experience in SoC or ASIC physical design Hands-on RTL-to-GDSII experience in 3nm or below, including floorplanning, physical synthesis, placement, clock tree synthesis, routing, static timing analysis, and signoff Experience with low-power implementation techniques, including power gating, voltage areas/islands, UPF, and DVFS Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners/modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects Experience working with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent Proficiency in scripting (TCL, Python, or Perl) and reading Verilog netlists/RTL Experience collaborating across RTL, DV, DFx, package, and vendor teams Ownership of block-level and/or full-chip power grid planning: dedicated macro supplies, power-switch chaining, MiM/decoupling caps, and EM/IR closure Track record of defining signoff criteria and leading tapeout execution Tapeout experience at 3nm or below Experience adhering to and implementing responsible, ethical AI practices (e.g. prompt/context engineering, agent orchestration) and staying current with emerging AI technologies Background in physically-aware synthesis of ultra-low-power designs, including custom recipes and app options, low-voltage PPA exploration, and UPF authoring Management of the die area budget, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion Facility with advanced clock-tree synthesis, such as multi-source / H-tree, at block- and/or chip-level, including clock power reduction and hierarchical techniques Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs Experience with 3D-IC structures (e.g., TSVs), EDA tools, and signoff methodologies Master's or PhD degree in Electrical Engineering, Computer Engineering, or equivalent areaMeta builds technologies that help people connect, find communities, and grow businesses.