Duties: Provide technical leadership in the sales and support of a wide range to Functional Verification technologies for Company's EDA leading edge customers in Silicon Valley; Integrates DVT products and services (at the block/chip/system level) and ensures expected behavior in customer's environments; Perform assessments of customer environments and requirements, providing expertise on topics such as: Verification planning, Testbench development using SV/UVM methodologies, Failure analysis and resolution, Coverage analysis, RTL/Gate- simulations performance optimization and competitive replacement, Regression debug and other flow/infrastructure development and testing; Accountable for the uncovering, scoping, and technical validity of the solutions to achieve the customer's design and verification objectives; Keeps other technical peers (country wide) informed of new and emerging technologies, share best practices and information; Become a trusted advisor to customer's business problems and eventually earns the trust to influence customer's decision process and business objectives; Articulate customer's technical needs and requirements to product engineering, influence and shape product direction; Deliver ongoing customer training classes and consulting related to advance verification topics, as well as assist in driving the adoption of these into customer design and verification process, participate in developing technical white papers, attend local and regional technical seminars and technology conferences to educate and promote DVT solutions and network with attendees. Position requires experience in the following: Designing and implementing digital logic using HDLs (Verilog, VHDL), HVLs (SystemVerilog/UVM, OVM, AVM, Vera, Specman, OOP), SystemC, and applying verification methodologies such as directed testing, constrained random testing, UPF, coverage modeling, and assertionbased verification.