Senior Applied Scientist, Superconducting Digital and Cryogenic Control Electronics,Center for Quantum Computing, Physical Design and Simulation, Enabling Technologies Amazon.com IncSenior Applied Scientist, Superconducting Digital and Cryogenic Control Electronics,Center for Quantum Computing, Physical Design and Simulation, Enabling TechnologiesSan Francisco, CAControlling and reading out orders of magnitude more qubits than today"s systems demands rethinking where classical control lives and what technology implements it; you will design and model superconducting digital logic (e.g., single-flux-quantum-family circuits) and related cryogenic electronics, evaluate them against the wiring, power, and thermal budgets of a scaled system, and co-design control approaches with the qubit devices they serve. The Amazon Web Services (AWS) Center for Quantum Computing (CQC) is seeking a Senior Applied Scientist to research and design cryogenic control hardware for large-scale quantum processors, with an emphasis on superconducting digital circuits.
ASIC Engineer, Design Meta Platforms IncASIC Engineer, DesignSunnyvale, CABachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design Microarchitecture, RTL coding, SoC integration and micro-architecture development Demonstrated communication and collaboration skills Master's or PhD degree in Electrical Engineering, Computer Science or related areas Experience in CPU, NOC, Memory, Die-to-die and Peripheral Subsystems Experience with Synthesis, Timing Closure and Formal Verification Methodology Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks and resets within SOC architecturesMeta builds technologies that help people connect, find communities, and grow businesses. You will collaborate with world-class researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
Senior Design Verification CAD Engineer, Silicon, Google Cloud Google LLCSenior Design Verification CAD Engineer, Silicon, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Senior ASIC Design Verification Engineer, Google Cloud Google LLCSenior ASIC Design Verification Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewASIC Design Verification Manager, TPU Compute Google LLCASIC Design Verification Manager, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments.
Senior ASIC Cloud Design Verification Engineer Google LLCSenior ASIC Cloud Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving team behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewRTL Design Engineer, TPU Compute Google LLCRTL Design Engineer, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewGFX/Display IP Digital Design Engineer Meta Platforms IncGFX/Display IP Digital Design EngineerSunnyvale, CAContribute to ASIC digital µArchitecture and design Assist performance/power analysis of the design and help meet power and performance targets Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test Develop micro-architecture, RTL coding, and design verification for complex IPs Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leadsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design µArchitecture, RTL coding, and micro-architecture development Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams Experience micro-architecting and designing IP with heavy fixed-point and/or floating-point data path logic Experience with synthesis, static timing analysis, and timing closure methodologies Experience collaborating with verification or physical design teams during the silicon development cycle Experience with microarchitecture and design optimization for power, performance, and area Experience with at least one procedural programming language (C, C++, Python, etc.) Experience with shell scripting (bash and/or csh) Experience with CDC and RDC analysis Experience with pixel processing pipelines like 2D/3D GFX engines and/or display processing units Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements) Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews) Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologiesMeta builds technologies that help people connect, find communities, and grow businesses. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
Senior Digital Design Engineer Ethan Alexander GroupSenior Digital Design EngineerSanta Clara, CaliforniaAs a Senior Logic Design Engineer, you will be responsible for: Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD). Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
NewRTL Design Engineer, TPU Google LLCRTL Design Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
ASIC Design Verification Manager, Google Cloud Google LLCASIC Design Verification Manager, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Guide the functional verification team for portions of TPU designs, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing functional verification infrastructure across subchip, subsystem, and fullchip level environments.
2027 Masters Hardware Design Verification Engineering Co-op/Intern Advanced Micro Devices, Inc2027 Masters Hardware Design Verification Engineering Co-op/InternSan Jose, CaliforniaWe are seeking a highly motivated Hardware Design Verificaon engineering intern/co-op to join our team and work towards design, built, and delivery of AMD’s high-end Machine Intelligence products. If you have knowledge / experience with any of the following technical skills (or related areas) and are enthusiastic about this role, we strongly encourage you to apply – Programming languages and scripts such as C++ /Python /C /Perl /Shell /UVM.
IC/RTL Design Engineer LumilensIC/RTL Design EngineerSan Jose, CaliforniaPower- and timing-aware design — managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks. You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end.
Sr. Staff CPU Physical Design CAD Engineer Qualcomm IncSr. Staff CPU Physical Design CAD EngineerSanta Clara, CA$198,700–$298,100 / yearMinimum Qualifications: Bachelor''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Sr. Staff Engineer, ASIC Design Ayar Labs IncSr. Staff Engineer, ASIC DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
SoC Digital Design Engineer, Multimedia Lab TikTok IncSoC Digital Design Engineer, Multimedia LabSan Jose, CACross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Senior Design Verification Engineer Hewlett Packard Enterprise CoSenior Design Verification EngineerSunnyvale, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
Senior Design Verification Engineer Hewlett Packard EnterpriseSenior Design Verification EngineerSunnyvale, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
Sr. Staff Engineer, Analog/Mixed-Signal Design Ayar Labs IncSr. Staff Engineer, Analog/Mixed-Signal DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others.
Senior SoC Digital Design Engineer, Multimedia Lab TikTok IncSenior SoC Digital Design Engineer, Multimedia LabSan Jose, CACross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.