KEY RESPONSIBILITIES: Drive the definition, development, and execution of industry-leading functional and performance verification and validation strategies, encompassing verification planning, testbench architecture, development of verification collaterals, debug methodologies, and coverage closure across IP, subsystem, and SoC programs within AECG and AMD. Work closely with architecture, design, and verification leaders to identify emerging challenges, align on requirements, and develop scalable verification methodologies that improve quality, efficiency, and predictability across future products.