ASIC Design Manager, Silicon and Systems Group Amazon.com Services LLCASIC Design Manager, Silicon and Systems GroupBoise, IDStrong expertise in the ASIC design flow, including microarchitecture development, RTL design, IP creation and integration, constraints development, synthesis, timing analysis, power analysis, and ECO flows. - Own the front-end ASIC design process including micro-architecture, RTL design, IP selection, IP creation, synthesis, timing constraints, power intent, and documentation.
Senior ASIC Physical Design Engineer Johns Hopkins Applied Physics Laboratory (APL)Senior ASIC Physical Design EngineerLaurel, MD$105,000–$290,000 / yearWe leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks.
ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs Annapurna Labs (U.S.) Inc.ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna LabsCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. • Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration Annapurna Labs (U.S.) Inc.ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning AccelerationAustin, TXAs a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. • Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs Annapurna Labs (U.S.) Inc.Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna LabsAustin, TXIn this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation.
ASIC Engineer, Annapurna Labs Amazon.com Services LLCASIC Engineer, Annapurna LabsAustin, TXAs a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. - Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
NewASIC Physical Design vaaridatechASIC Physical DesignSan Jose, CA, CATemporaryContractorFull time5in"> Understanding and experience of mixed signal environments is a must. Regards Manju Sharma (Business Unit Head) Vaarida Technologies 📧 Email: manju@vaaridatech.com Here is an ASIC Physical Design role MUST be onsite in the Bay Area though if you can find candidates that are already there…. Spots: Position 1: Location: Onsite, San Jose, CA Duration: 6-9+ Months (will extend) Interview Process: 1 phone, 1 panel onsite 1 zoom Skills/JD: Physical Design engineer to own the entire block Floorplanning, PlacenRoute, Timing Closure DRC/LVS checks Low nm experience preferred Cadence tooling - They are using Innovus and Voltus mostly Synopsys tools for Timing Analysis I have summarized the job requirements below: <span style="tab-stops:list.
ASIC Test Engineer, Annapurna Silicon Operations Annapurna Labs (U.S.) Inc.ASIC Test Engineer, Annapurna Silicon OperationsAustin, TXAs our final product is a server, not just the silicon, you will find yourself stretching beyond structural testing and incorporating a lot more mission profile testing, utilizing a variety of external controlling ICs, porting server management and customer run-time software, including the use of virtualized machines and specific microcontrollers found in the end application. Annapurna Labs develops the silicon used in our most advanced machine learning accelerator servers, utilizing the latest process nodes and massively scaled server clusters to provide the best hardware platform to customers for both inference and training workloads.
Analog Electronics Design Engineer for Space Instruments Johns Hopkins Applied Physics Laboratory (APL)Analog Electronics Design Engineer for Space InstrumentsLaurel, MD$100,000–$245,000 / yearOur group of approximately 40 engineers brings technical expertise across all aspects of instrument development, including systems engineering, digital and analog electronics design, FPGA design, and software design. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development.
DFT (Design for Test) Engineer Plugins IncDFT (Design for Test) EngineerSanta Clara, CA$50–$90 / hourContractorFull timeWe are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug.
Sr. DFT Design Engineer, AWS Machine Learning Acceleration Annapurna Labs (U.S.) Inc.Sr. DFT Design Engineer, AWS Machine Learning AccelerationAustin, TXAs a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs.
SOC Top Level Physical Design Engineer, Annapurna Labs Annapurna Labs (U.S.) Inc.SOC Top Level Physical Design Engineer, Annapurna LabsCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation.
Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning Annapurna Labs (U.S.) Inc.Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine LearningCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.
Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning Annapurna Labs (U.S.) Inc.Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine LearningCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.
DFT Design Engineer, Machine Learning Acceleration Annapurna Labs (U.S.) Inc.DFT Design Engineer, Machine Learning AccelerationAustin, TXAs a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. We're looking for an ASIC DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs.
Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging Annapurna Labs (U.S.) Inc.Package Layout Design Engineer , Annapurna Labs - AI Silicon PackagingTempe, AZIn this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets. - Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
Sr. Signal Integrity and Power Integrity Engineer, Amazon Leo Amazon Kuiper Manufacturing Enterprises LLCSr. Signal Integrity and Power Integrity Engineer, Amazon LeoRedmond, WASignal Integrity and Power Integrity Engineer, you will be responsible for developing SIPI collateral supporting system integration of the latest technology, defining and developing Signal and Power Integrity test methodologies, participating in design reviews, performing SI and PI simulations, providing reports, collaborating with other engineers, validating your designs in the lab, and working to ensure a high technical bar for hardware designs across Amazon Leo. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Physical Design Engineer II (IC) Arrow Electronics, Inc.Physical Design Engineer II (IC)San Jose, CA$87,400–$165,000 / yearContribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
Lead Firmware Engineer GCR Professional ServicesLead Firmware EngineerWoburn, MassachusettsContractorOur clients System Development Division (SDD) is focused on delivering National Defense capabilities by driving mission-focused strategies to develop advanced technology systems enabling enduring products and solutions focused on achieving the customer vision. Applicants are expected to be self-motivated, detail oriented and have a demonstrated ability to effectively communicate with all levels of management and individual contributors on the program team through strong written and verbal communication skills.?.
NewElectrical Engineer/ Senior Electrical Engineer Aminov Search PartnersElectrical Engineer/ Senior Electrical EngineerRonkonkoma, NY$100,000 / yearWe are looking for a proficient expert in circuit and systems engineering with substantial experience in designing analog/mixed-signal circuits, motion control systems, and power electronics. • Acumen in power electronics-related fields, including DC/DC converters and motor drive circuits leveraging technologies like MOSFET, IGBT, SiC, or GaN.