Principal Analog Mixed Signal ASIC Layout Engineer GCR Professional ServicesPrincipal Analog Mixed Signal ASIC Layout EngineerCambridge, MassachusettsRemoteContractorA successful candidate will assist ASIC development through creating custom analog layouts, floor planning entire chips, high level problem solving, and executing tape outs. ¿ Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitic, contribute to design-for-test development.
Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning Annapurna Labs (U.S.) Inc.Sr. Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine LearningCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of Hardware in our data centers including technologies such as AWS Inferentia which is a machine learning inference product designed to deliver high performance at low cost. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.
Hardware Design Engineer - Aerospace Industry JobotHardware Design Engineer - Aerospace IndustryWest Chester, OH$100,000–$110,000 / yearInformation collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal. Our teams specialize in building advanced hardware that supports critical systems across industries like aerospace, defense, and communications with a strong emphasis on innovation, quality, and collaboration.
DFT Engineer (Design for Test) Plugins IncDFT Engineer (Design for Test)Santa Clara, CAContractorFull timeIn this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices. We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.
Physical Design Engineer Einfochips (An Arrow electronics company)Physical Design EngineerSan Jose, CA$110,000–$130,000 / yearContractorFull timeContribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Lead Firmware Engineer GCR Professional ServicesLead Firmware EngineerWoburn, MassachusettsContractorOur clients System Development Division (SDD) is focused on delivering National Defense capabilities by driving mission-focused strategies to develop advanced technology systems enabling enduring products and solutions focused on achieving the customer vision. Applicants are expected to be self-motivated, detail oriented and have a demonstrated ability to effectively communicate with all levels of management and individual contributors on the program team through strong written and verbal communication skills.?.
Professional Structural Engineer P.E. NucorProfessional Structural Engineer P.E.Lathrop, CA$103,000–$137,000 / yearWith multiple locations throughout the United States, NBG is proud to design world-class building solutions tailored to meet the needs of any market including commercial, industrial, agricultural, and institutional. Nucor Buildings Group is searching for individuals who can contribute to our sales growth and profitability by creating safe, accurate, and cost-effective metal building systems.
NewProfessional Structural Engineer NucorProfessional Structural EngineerBrigham City, UTWith multiple locations throughout the United States, NBG is proud to design world-class building solutions tailored to meet the needs of any market including commercial, industrial, agricultural, and institutional. Nucor Buildings Group (NBG), a proud Nucor product group, is one of North America’s largest and most experienced manufacturers of metal building systems.
NewFPGA Engineer ( Rochester, NY ) 36890 TalentPro ConsultingFPGA Engineer ( Rochester, NY ) 36890Rochester, NYExperience in FPGA/ASIC development using VHDL or Verilog · Experience in FPGA/ASIC verification using System Verilog · Experience with integrating FPGA firmware on hardware · Experience with FPGA Vendor Specific FPGA Implementation tools (Vivado/Quartus/Libero) · Experience working in a Linux based development environment Preferred Additional Skills: · Experience with MatLab, Simulink or similar digital signal processing (DSP) modelling tools · Experience in communication system signal processing theory and waveform design · Experience with TCL or Python scripting languages · Working knowledge and experience in implementation and testing of MODEM RF Designs · Experience with Universal Verification Methodology (UVM) · Working knowledge and experience with vendor specific FPGA verification tools (Mentor Questa, Visualizer) Candidate will be required to analyze requirements, create FPGA specifications/development plans, create FPGA verification/test plans, code firmware designs in VHDL, code test benches in System Verilog, and verify designs meet requirements.
NewSenior Quantum Engineer - Digital Control Systems MicrosoftSenior Quantum Engineer - Digital Control SystemsRedmond, WA$119,800–$234,700 / yearBachelor’s degree in Electrical Engineering, Computer Engineering, or related field and 6+ years of technical engineering experience OR Master’s degree in Electrical Engineering, Computer Engineering, or related field and 4+ years of technical engineering experience. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Principal ASIC Design Engineer Atom Computing, Inc.Principal ASIC Design EngineerBoulder, CO$180,000–$220,000 / yearYou will partner closely with customers and cross-functional teams to translate evolving requirements into production-ready designs, ensuring alignment between technical execution and business objectives. Work closely with Atom Computing's quantum physicists, optical engineers, hardware and software engineers to understand use cases and deliver hardware that addresses the needs.
FPGA/ASIC Design Engineer Silicon Engineering Space Exploration Technologies CorpFPGA/ASIC Design Engineer Silicon EngineeringRedmond, WA$125,000–$145,000 / yearParticipate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation. Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.
Principal ASIC Design Engineer Starshield Space Exploration Technologies CorpPrincipal ASIC Design Engineer StarshieldHawthorne, CA$200,000–$285,000 / yearYou will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Sr. ASIC Design Engineer Starshield Space Exploration Technologies CorpSr. ASIC Design Engineer StarshieldHawthorne, CA$160,000–$225,000 / yearYou will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Staff ASIC Design Engineer Celero CommunicationsStaff ASIC Design EngineerSan Jose, CaliforniaCelero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.) .
NewSenior Digital ASIC Design Engineer Brookhaven National LaboratorySenior Digital ASIC Design EngineerUpton, New YorkWe are engaged in the development of ASICs for particle detectors, high-resolution X- and gamma-ray spectrometers, high-rate photon counters and imagers, cryogenic and radiation-tolerant instrumentation, and other specialized systems for high-energy physics, nuclear physics, photon sciences, quantum information science, and related scientific programs. The successful candidate will contribute to microelectronics for the Electron-Ion Collider (EIC), including ePIC detector systems, while also supporting ASICs for other programs in high-energy physics, nuclear physics, photon sciences, quantum information science, and related instrumentation efforts at BNL and with external partners.
ASIC Design Engineer Hewlett Packard Enterprise CompanyASIC Design EngineerSunnyvale, CAFull timeAccountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
Senior ASIC Design Engineer Zp Group LlcSenior ASIC Design EngineerSaratoga, CA$250,000–$290,000 / yearKeywords: ASIC, ASIC Architect, Networking ASIC, AI Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC. Qualifications for Senior ASIC Design Engineer: 10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc).
Digital ASIC Design Engineer for Mixed-Signal IPs Qualcomm IncDigital ASIC Design Engineer for Mixed-Signal IPsSan Diego, CA$115,600–$173,400 / yearGeneral Summary: The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs - including DAC, ADC, and PLLs - for integration across Qualcomm's product portfolio. 2+ years of hands-on experience in RTL design and ASIC implementation of mixed-signal IPs such as SerDes DDR PHY, PLLs, DACs, ADCs, and sensors.
Senior ASIC Physical Design Engineer Johns Hopkins Applied Physics LaboratorySenior ASIC Physical Design EngineerLaurel, MarylandFull timeWe leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks.
ASIC Design Engineer lll Hewlett Packard EnterpriseASIC Design Engineer lllSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. The successful candidate will be responsible for the microarchitecture, RTL implementation, integration, and bring-up of high-performance networking IPs and subsystems used in next-generation switch, router, SmartNIC, DPU, and AI networking products.
Sr. Engineer, ASIC Design Ayar LabsSr. Engineer, ASIC DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
ASIC Design Engineer lll Hewlett Packard Enterprise CoASIC Design Engineer lllSunnyvale, CA$120,000–$243,000 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
ASIC Design Engineer Qualcomm IncASIC Design EngineerSanta Clara, CA$126,700–$190,100 / yearQCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. Required Skill: 5+ years of industry experience in ASIC design, micro-architecture, and design integration, Strong background in SoC micro-architecture, including specification, definition, and implementation of functional blocks.
ASIC Design Engineer Hewlett Packard EnterpriseASIC Design EngineerSunnyvale, CaliforniaAccountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more} What We Can Offer You: Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
Principal ASIC Design Engineer Hewlett Packard EnterprisePrincipal ASIC Design EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
Sr. ASIC Design Engineer MicronSr. ASIC Design EngineerSan Jose, CaliforniaAs a Senior ASIC Design Engineer and domain expert, you will perform logic design across the full ASIC lifecycle from specifications and microarchitecture to design, integration, synthesis, timing, linting, and CDC. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Principal ASIC Design Engineer Hewlett Packard Enterprise CoPrincipal ASIC Design EngineerSunnyvale, CA$174,000–$352,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
Principal Digital Design Engineer - ASIC and FPGA GreenWave RadiosPrincipal Digital Design Engineer - ASIC and FPGAIrvine, CA$190,000–$225,000 / yearOur cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. You'll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software.
Sr. ASIC Design Engineer Hewlett Packard EnterpriseSr. ASIC Design EngineerRoseville, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
Sr. ASIC Design Engineer Hewlett Packard Enterprise CoSr. ASIC Design EngineerRoseville, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
ASIC Design Engineer III ArcfieldASIC Design Engineer IIIHome, New YorkFull timeThere are differentiating factors that can impact a final salary/hourly rate, including, but not limited to, Contract Wage Determination, relevant work experience, skills and competencies that align to the specified role, geographic location (For Remote Opportunities), education and certifications as well as Federal Government Contract Labor categories. Our solution areas include space mission engineering, atmospheric science, digital engineering, mission assurance, and advances in modeling and simulation that together with our enterprise-wide adoption of artificial intelligence and machine learning, lead to better systems and timely, reliable decision-making.
Sr. Engineer, ASIC Design Ayar Labs IncSr. Engineer, ASIC DesignSan Jose, CA$160,000–$192,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
ASIC Design Engineer (Video Silicon IP) - Multimedia Lab Beijing ByteDance Technology Co LtdASIC Design Engineer (Video Silicon IP) - Multimedia LabSan Jose, CAThe successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Team Introduction The Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users.
Sr. ASIC Design Engineer (Video Silicon IP) - Multimedia Lab Beijing ByteDance Technology Co LtdSr. ASIC Design Engineer (Video Silicon IP) - Multimedia LabSan Jose, CAThe successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer Qualcomm IncNext-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design EngineerSan Diego, CA$140,000–$210,000 / yearNext Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory subsystems. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products.
ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration Amazon.com IncASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning AccelerationCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
Senior Analog/Mixed Signal ASIC Design Engineer The Charles Stark Draper LaboratorySenior Analog/Mixed Signal ASIC Design EngineerCambridge, MassachusettsTypical responsibilities include creating top level and circuit-level specifications, developing conceptual circuit designs, reviewing detailed block-level designs during implementation, conducting chip level-planning with implementation team, and providing inputs to verification and test planning. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities.
Sr. Staff Engineer, ASIC Design Ayar LabsSr. Staff Engineer, ASIC DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
ASIC Design Engineer (eInfochips) Arrow Electronics IncASIC Design Engineer (eInfochips)Mountain View, CAAlong with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.
SR ASIC SoC Design Engineer Advanced Micro Devices IncSR ASIC SoC Design EngineerSanta Clara, CAWe are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production. THE TEAM: Our group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads.
Cellular ASIC Design Engineer - Protocols Apple IncCellular ASIC Design Engineer - ProtocolsCAYou will own the full lifecycle from early architectural exploration and HW/SW partitioning, through RTL implementation, to silicon bring-up and lab validation. Were looking for a Cellular ASIC Design Engineer, where you will architect and implement protocol processing hardware for next-generation wireless SoCs.
ASIC Design Engineer - Neural Engine DMA Apple IncASIC Design Engineer - Neural Engine DMASunnyvale, CAANE DMAs scale and complexity means grappling with: decomposing tensor surfaces into efficient fetch sequences; maximizing throughput under real-world memory system conditions; maintaining data consistency across concurrent streams; multi-level arbitration and ordering correctness; sizing latency-tolerant buffering structures; and security and state isolation. In this front-end design role, your work will include: Taking end-to-end ownership of DMA subsystems through the full cycle: microarchitecture specification, RTL implementation, front-end signoff (synthesis, timing closure, area and power analysis, linting, LEC), and design verification closure.
ASIC Design Engineer Apple IncASIC Design EngineerBeaverton, ORHands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable. Ability to communicate optimally across all internal groups Familiarity with software and operating concepts a plus Familiarity with scripting languages like Perl, Python, or TCL a plus.
ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs Amazon.com IncASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna LabsCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
ASIC Design Verification Engineer Positron AIASIC Design Verification EngineerNY$200,000–$350,000 / yearYou will be responsible for developing and executing advanced verification methodologies, working closely with design, architecture, and software teams to validate our silicon solutions. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.
Senior ASIC Design Engineer Cornelis Networks IncSenior ASIC Design EngineerAustin, TXRemoteCornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.
Sr. Staff ASIC Design Verification Engineer RivianSr. Staff ASIC Design Verification EngineerPalo Alto, California$237,000–$296,000 / yearFull timeRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services.
ASIC Design Verification Engineer Waymo LLCASIC Design Verification EngineerMountain View, CA$175,000–$215,000 / yearSince its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World''s Most Experienced Driver-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.
ASIC Design and Verification Engineer - AI Analog DevicesASIC Design and Verification Engineer - AIWilmington, MassachusettsSVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire design verification landscape - including Unified Metric-Driven Verification (MDV), System Verilog (SV)/UVM-based methodologies, Mixed-Signal DV, Post-Silicon Validation Shift-Left, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies. In this role, you will leverage your knowledge in Integrated Circuit (IC) design and verification with working knowledge of AI/ML to develop, integrate, deploy, and support best-in-class Agentic AI solutions including custom instructions, skills and automation scripts.