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ASIC Design Engineer Jobs in the United States

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Jobs

ASIC Design Engineer Intern Hewlett Packard Enterprise Co

Sunnyvale, CA

$35–$41 / hour

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Impact/Scope: University students actively enrolled in a university/college/institution pursuing a Bachelor's degree in a technical area of study, and who typically works during school breaks and then returns to their university.

20 days ago

Principal Asic Design Engineer - Chip Lead CesiumAstro

Aliso Viejo, CA

The ideal candidate will have knowledge in all or most of the following areas: digital communications systems, DSP, ASIC microacrchitecture, analog IP integration, embedded processors, high level verification, RTL design with multiple asynchronous clock domains, timing analysis, DFT, backend flow, chip bring up, debug, lab testing, and transitioning a product from first sample through release to volume production. Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.

4 days ago

ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) Teradyne Inc

North Reading, MA

$98,700–$157,900 / year

The primary focus of this role is FPGA verification, working closely with cross‑functional teams to deliver high‑quality, robust designs. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

27 days ago

ASIC Design Verification Engineer (Security Group) - Sr Staff Qualcomm Inc

Santa Clara, CA

$190,200–$285,400 / year

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Writes detailed technical documentation (e.g., feature descriptions, architectural descriptions, verification test plans, and implementation details, etc.) for highly complex secure subsystem designs; reviews documentation of junior engineers.

4 days ago

Asic/Fpga Design Verification Engineer (Teradyne, N. Reading, MA) Teradyne, Inc.

North Reading, MA

$98,700–$157,900 / year

27 days ago

Senior Asic Design Verification Engineer Ethernovia

San Jose, CA

$200,000–$300,000 / year

Join Ethernovia's team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. We are well-funded and backed by some of the worlds' leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date: Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips.

30+ days ago

ASIC Design Engineer - SoC Interconnect, Cache & Memory Systems Qualcomm Inc

San Diego, CA

$101,400–$152,200 / year

We are seeking talented ASIC Design Engineers to contribute to the architecture, microarchitecture, design, and deployment of next-generation SoC Interconnects, Cache and Memory Subsystems, and High-Speed DDR Memory Controllers. In this role, you will work closely with architecture, verification, physical design, and software teams to develop high-performance, power-efficient silicon solutions that enable Qualcomm''s most advanced products.

5 days ago

ASIC Board Design Engineer - System Lead, PCB Layout, Signal Integrity, and System Architecture (Onsite) Cisco Systems Inc

Milpitas, CA

$194,600–$285,700 / year

Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Strategic Leadership & Delivery: Experience leading complex, multi-site, and cross-functional engineering initiatives, partnering with silicon vendors and contract manufacturers to solve high-impact, ambiguous technical challenges at scale.

14 days ago

Asic & Fpga Design Engineer - E2 Lockheed Martin Corporation

Sunnyvale, CA

$91,200–$169,400 / year

The Silicon Solutions team of Lockheed Martin Space is building the best ASIC/FPGA team in the world, and are seeking a highly talented and motivated ASIC & FPGA Design Engineer who has a passion for microchip design and space. To be effective in this role, you will need: You need to be an independently minded and well organized engineer, comfortable in laboratory digital environments, and able to respond and interact with a dynamic fast-moving team.

14 days ago

Senior ASIC (Front-End) Design Engineer Ethernovia

San Jose, California

$200,000–$300,000 / year

Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital). As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals.

30+ days ago

Senior Asic (Front-End) Design Engineer Ethernovia

San Jose, CA

$200,000–$300,000 / year

Summary: As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design, from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis to deliver a design meeting target power, performance, and area goals. Join Ethernovia's team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines.

30+ days ago

Senior ASIC Design Verification Engineer Ethernovia

San Jose, California

$200,000–$300,000 / year

Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire (financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital). Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines.

30+ days ago

ASIC / FPGA Design Verification Engineer – (Lead or Senior) Boeing

El Segundo, California

$146,200–$197,800 / year

Engineers support ASIC, FPGA, and SoC verification activities across advanced aerospace programs including space systems, satellite technologies, NASA mission support, Space Launch System (SLS) technologies, aviation platforms, communications systems, autonomous systems, and related digital subsystems. Senior (Level 5): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g.

16 days ago

Sr. Asic Layout Design Engineer Teledyne Technologies

US - Goleta, CA

$113,600–$151,400 / year

As part of our close-knit team, you will play a key role in producing analog and mixed-signal circuit layouts by preparing multi-dimensional, detailed drawings of the semiconductor devices from schematics provided by design engineering. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research.

30+ days ago

FPGA/ASIC Design & Analysis Engineer Level 5 Indotronix International Corporation

El Segundo, CA

$96.72–$121.15 / hour

Required Skills: • 5+ years of FPGA and/or ASIC design experience; • strong Xilinx/AMD Vivado experience; • Experience with Versal family devices; • Verilog/SystemVerilog HDL proficiency required; • Advanced FPGA implementation skills (synthesis, timing closure, constraints); • Active U.S. security clearance. • Recruiters should prioritize candidates who can clearly explain their personal technical contributions, design decisions, debugging approach, and ownership of deliverables, rather than simply listing tools or technologies used on a project.

2 days ago

Senior ASIC Design Verification Engineer - Slingshot Hewlett Packard Enterprise

Bloomington, Wisconsin

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.

8 days ago

Asic Design Engineer (Silicon Engineering) Space Exploration Technologies

Palo Alto, CA

$135,000–$175,000 / year

Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation. Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.

18 days ago

ASIC Design Engineer (Silicon Engineering) SpaceX

Palo Alto, CA

$135,000–$175,000 / year

18 days ago

Senior Asic Design Engineer - Agentic AI Nvidia

Durham, NC

What you'll be doing: As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

3 days ago

Senior Asic Design Verification Engineer - LPU Nvidia

Austin, TX

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

3 days ago

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ASIC Design Engineer Jobs in the United States

ASIC Design Engineer Intern Hewlett Packard Enterprise Co

Principal Asic Design Engineer - Chip Lead CesiumAstro

ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) Teradyne Inc

ASIC Design Verification Engineer (Security Group) - Sr Staff Qualcomm Inc

Asic/Fpga Design Verification Engineer (Teradyne, N. Reading, MA) Teradyne, Inc.

Senior Asic Design Verification Engineer Ethernovia

ASIC Design Engineer - SoC Interconnect, Cache & Memory Systems Qualcomm Inc

ASIC Board Design Engineer - System Lead, PCB Layout, Signal Integrity, and System Architecture (Onsite) Cisco Systems Inc

Asic & Fpga Design Engineer - E2 Lockheed Martin Corporation

Senior ASIC (Front-End) Design Engineer Ethernovia

Senior Asic (Front-End) Design Engineer Ethernovia

Senior ASIC Design Verification Engineer Ethernovia

ASIC / FPGA Design Verification Engineer – (Lead or Senior) Boeing

Sr. Asic Layout Design Engineer Teledyne Technologies

FPGA/ASIC Design & Analysis Engineer Level 5 Indotronix International Corporation

Senior ASIC Design Verification Engineer - Slingshot Hewlett Packard Enterprise

Asic Design Engineer (Silicon Engineering) Space Exploration Technologies

ASIC Design Engineer (Silicon Engineering) SpaceX

Senior Asic Design Engineer - Agentic AI Nvidia

Senior Asic Design Verification Engineer - LPU Nvidia

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