1,605 Results for

ASIC Design Engineer Jobs in California

Jobs

Saratoga, CA30+ days ago

Full-time

If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips.

Los Angeles, CA7 days ago

$100,000–$130,000

Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant field plus 4 years of demonstrated experience in FPGA design and testing/verification OR 2 years of FPGA experience in design and testing/verification with an MS or advanced degree. The successful individual in this role will participate in the design, simulation, prototyping, and testing of wireless communication and sensing projects and products.

Palo Alto, CA30+ days ago

$210,000–$295,000 Per Year

You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.

Palo Alto, CA30+ days ago

$170,000–$235,000 Per Year

Irvine, California13 days ago

Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. Strong knowledge of Digital Signal Processing (DSP), Digital Communication, and Forward Error Correction (FEC) techniques.

Sunnyvale, CA30+ days ago

Full-time

Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.

Sunnyvale, California19 days ago

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. The successful candidate will be responsible for the microarchitecture, RTL implementation, integration, and bring-up of high-performance networking IPs and subsystems used in next-generation switch, router, SmartNIC, DPU, and AI networking products.

Hawthorne, CA14 days ago

$125,000–$150,000 Per Year

Sunnyvale, CA30+ days ago

$120,000–$243,000 Per Year

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Sunnyvale, CA30+ days ago

$174,000–$352,500 Per Year

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.

Sunnyvale, CA30+ days ago

$120,000–$243,000 Per Year

Additional Skills: Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.

Sunnyvale, California30+ days ago

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.

Sunnyvale, California30+ days ago

Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}What We Can Offer You: Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.

San Jose, CA30+ days ago

Knowledge of ARM architecture and AMBA protocol specifications Familiarity with PCIe or CXL transaction layer protocols Experience with low-power design techniques (clock gating, power gating, voltage scaling) Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting Exposure to formal verification tools for equivalence checking and property verification Familiarity with AI-assisted design tools and modern EDA technologies Experience mentoring junior engineers and leading design teams Strong technical writing skills for design specifications and documentation Excellent communication and collaboration skills in cross-functional environments. RTL Design & Microarchitecture: • Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.

Roseville, CA30+ days ago

$153,500–$310,500 Per Year

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.

Roseville, California30+ days ago

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.

San Jose, CA30+ days ago

$160,000–$192,000 Per Year

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.

San Jose, California17 days ago

As a Senior ASIC Design Engineer and domain expert, you will perform logic design across the full ASIC lifecycle from specifications and microarchitecture to design, integration, synthesis, timing, linting, and CDC. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

San Jose, CA30+ days ago

We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary.

Palo Alto, CA30+ days ago

$210,000–$295,000 Per Year

Hawthorne, CA30+ days ago

$160,000–$225,000 Per Year

Santa Clara, CA30+ days ago

As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.

Santa Clara, California30+ days ago

As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.

Santa Clara, CA30+ days ago

California, CA30+ days ago

You will own the full lifecycle from early architectural exploration and HW/SW partitioning, through RTL implementation, to silicon bring-up and lab validation. We're looking for a Cellular ASIC Design Engineer, where you will architect and implement protocol processing hardware for next-generation wireless SoCs.

Hawthorne, CA30+ days ago

$160,000–$225,000 Per Year

The Lead ASIC Design Verification Engineer will lead a team that supports custom ASICs and FPGAs design for cutting edge satellites systems that deliver unprecedented quantities of data at unheard of speeds to the service-members who defend our Nation and Allies. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.

Sunnyvale, CA30+ days ago

$170,000–$240,000 Per Year

ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).

San Jose, California13 days ago

As a Staff Engineer, you will own critical High speed interface IP, drive methodology improvements (such as AI-assisted design flows), and mentor engineers to ensure first-pass silicon success. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions.

Saratoga, CA14 days ago

$250,000–$290,000 Per Year

Keywords: ASIC, ASIC Architect, Networking ASIC, AI Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC. Qualifications for Senior ASIC Design Engineer: 10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc).

San Jose, CA30 days ago

$180,000–$223,000 Per Year

Sunnyvale, CA28 days ago

$170,000–$230,000 Per Year

San Jose, CA16 days ago

$163,000–$253,000 Per Year

Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support.

California30+ days ago

Experience in micro-architecture of complex custom/ASIC products, focusing in one or more of the following areas: NPU, embedded processors, DSP, graphics, and general-purpose microprocessors. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.

Mountain View, CA13 days ago

$175,000–$215,000 Per Year

Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World''s Most Experienced Driver-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.

Palo Alto, California30+ days ago

$237,000–$296,000 Per Year

Santa Clara, CA30+ days ago

Knowledge of high-performance memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram interface calibration/training mechanisms and algorithms is a plus. As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day.

Cupertino, CA30+ days ago

As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine. Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects.

Santa Clara, CA30+ days ago

As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation.

Us, California30+ days ago

This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.

Sunnyvale, CA21 days ago

From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

San Jose, CA30+ days ago

$165,000–$241,400 Per Year

Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. ASIC design experience, delivering silicon from microarchitecture, specification, and RTL coding through tape-out with multiple ASIC tape-outs at advanced technology nodes.

CA30+ days ago

$168,000–$264,500 Per Year

This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.

Mountain View, CA27 days ago

Along with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.

San Jose, California30+ days ago

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

San Jose, CA30+ days ago

$165,000–$241,400 Per Year

Ciscos silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. For quota-based sales roles on Ciscos sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

Cupertino, CA30+ days ago

As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.

San Jose, California30+ days ago

Santa Clara, CA30+ days ago

You will work across the full development lifecycle-from architecture and microarchitecture definition through RTL implementation, integration, and silicon bring up-collaborating closely with architecture, verification, physical design, firmware, and software teams to deliver robust, scalable SoC solutions for next generation AI networking products. In this role, you will be a senior technical contributor responsible for designing and integrating complex SoC subsystems for AI networking ASICs, including both monolithic and chiplet based SoC architectures.

San Jose, California21 days ago

Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. For quota-based incentive pay, Cisco typically pays as follows: 75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and.

San Jose, California13 days ago

Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire(financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital). Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines.

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ASIC Design Engineer Jobs in California

RTL Engineer, Networking ASIC Vortexlink

R&D Engineer Gables Search Group

Principal ASIC Design Engineer Starshield Space Exploration Technologies Corp

Sr. ASIC Design Engineer Starshield Space Exploration Technologies Corp

ASIC Design Engineer - Staff Celero Communications

ASIC Design Engineer Hewlett Packard Enterprise Company

ASIC Design Engineer lll Hewlett Packard Enterprise

New Graduate Engineer, ASIC Design Starshield Space Exploration Technologies Corp

ASIC Design Engineer lll Hewlett Packard Enterprise Co

Principal ASIC Design Engineer Hewlett Packard Enterprise Co

ASIC Design Engineer Hewlett Packard Enterprise Co

Principal ASIC Design Engineer Hewlett Packard Enterprise

ASIC Design Engineer Hewlett Packard Enterprise

ASIC/SoC Design Engineer, RTL design for SoC IPs Advanced Micro Devices Inc

Sr. ASIC Design Engineer Hewlett Packard Enterprise Co

Sr. ASIC Design Engineer Hewlett Packard Enterprise

Sr. Engineer, ASIC Design Ayar Labs Inc

Sr. ASIC Design Engineer Micron

ASIC Design Engineer, ML Processor & Digital IP Advanced Micro Devices Inc

Principal ASIC Design Verification Engineer Starshield Space Exploration Technologies Corp

Sr. ASIC Design Verification Engineer Starshield Space Exploration Technologies Corp

SR ASIC Design Engineer - NoC & AXI Interconnect Advanced Micro Devices Inc

SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O Advanced Micro Devices, Inc

Principal ASIC Design Engineer - PCIe / High-Speed I/O Advanced Micro Devices Inc

Cellular ASIC Design Engineer - Protocols Apple Inc

Lead ASIC Design Verification Engineer Starshield Satellite Engineering Space Exploration Technologies Corp

Sr. ASIC Design Verification Engineer Silicon Engineering Space Exploration Technologies Corp

Staff Engineer, IP Design (ASIC) SK hynix memory solutions America

Senior ASIC Design Engineer Zp Group Llc

Sr. Staff Engineer, ASIC Design Ayar Labs Inc

Sr. SOC/ASIC Physical Design Engineer Silicon Engineering Space Exploration Technologies Corp

Staff Engineer, ASIC Design Verification Samsung Semiconductor

ASIC Design Engineer (All Levels) 31 MSI

ASIC Design Verification Engineer Waymo LLC

Sr. Staff ASIC Design Verification Engineer Rivian

ASIC Design Engineer Apple Inc

ASIC Design Engineer - Pixel IP DMA Apple Inc

ASIC Design Engineer - Cache Controller Apple Inc

Senior ASIC Design Engineer - Hardware NVIDIA

Senior ASIC Design Engineer, Google Cloud Google LLC

ASIC Design Engineer (Onsite) Cisco Systems Inc

Senior ASIC Design Engineer NVIDIA Corp

ASIC Design Engineer (eInfochips) Arrow Electronics Inc

Staff/Principal Engineer. ASIC Design Verification (DDR expert) Micron

ASIC Design Engineer Cisco Systems Inc

ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration Amazon.com Inc

ASIC Design STA Engineer Advanced Micro Devices, Inc

SR ASIC SoC Design Engineer Advanced Micro Devices Inc

ASIC Design Engineer Technical Lead Cisco Systems

Senior ASIC Design Verification Engineer Ethernovia

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