Principal Analog Mixed Signal ASIC Layout Engineer GCR Professional ServicesPrincipal Analog Mixed Signal ASIC Layout EngineerCambridge, MassachusettsRemoteContractorA successful candidate will assist ASIC development through creating custom analog layouts, floor planning entire chips, high level problem solving, and executing tape outs. ¿ Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitic, contribute to design-for-test development.
Lead Firmware Engineer GCR Professional ServicesLead Firmware EngineerWoburn, MassachusettsContractorOur clients System Development Division (SDD) is focused on delivering National Defense capabilities by driving mission-focused strategies to develop advanced technology systems enabling enduring products and solutions focused on achieving the customer vision. Applicants are expected to be self-motivated, detail oriented and have a demonstrated ability to effectively communicate with all levels of management and individual contributors on the program team through strong written and verbal communication skills.?.
Senior Analog/Mixed Signal ASIC Design Engineer The Charles Stark Draper LaboratorySenior Analog/Mixed Signal ASIC Design EngineerCambridge, MassachusettsTypical responsibilities include creating top level and circuit-level specifications, developing conceptual circuit designs, reviewing detailed block-level designs during implementation, conducting chip level-planning with implementation team, and providing inputs to verification and test planning. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities.
Staff Engineer, Digital ASIC Design (CONTRACT) Butterfly NetworkStaff Engineer, Digital ASIC Design (CONTRACT)Burlington, MAIdeally, you also have these skills/experiences/attributes (but it's ok if you don't!): Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline. Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces.
ASIC Design Engineer Marvell Technology IncASIC Design EngineerMAStrong background in high-performance DSP and high-speed datapath design, including pipelined arithmetic units, algorithm-driven hardware implementation, packet processing engines, memory subsystems, and large-scale control/state machines. • Drive post-silicon bring-up and debug, collaborating with lab and systems teams to validate functionality, characterize performance, and resolve complex issues across datapath, DSP, and protocol layers.
SoC/ASIC Design Verification Engineer zeroRISCSoC/ASIC Design Verification EngineerBoston, MassachusettszeroRISC zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers.
ASIC Digital Design Engineer-17369 Synopsys IncASIC Digital Design Engineer-17369MAThe Team You'll Be A Part Of: Join our R&D Professional team, specializing in mixed-signal ASIC development and supporting HBM/DDR PHY IP customers. What You'll Need: The ideal candidate will specialize in one of the following, experience in multiple areas would be a bonus: ASIC RTL design and verification experience.
Senior ASIC Hardware Design Engineer NVIDIA CorpSenior ASIC Hardware Design EngineerWestford, MAAs a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power GPU and interconnect subsystems. You will work closely with architects, design engineers, verification engineers, and physical design engineers to contribute to the design and development of next-generation NVLink protocol and GPU subsystem logic, delivering functional, performant, and physically implementable designs.
ASIC Design Engineer Broadcom IncASIC Design EngineerMA$108,000–$172,800 / yearJob Description: We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. Responsibilities Include: Participate in large complex design implementations using the latest technology nodes; lead one or more disciplines in design closure as part of the design team.
ASIC Digital Design, Staff Engineer -18138 Synopsys IncASIC Digital Design, Staff Engineer -18138MAWe partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.
ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) Teradyne IncASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)MA$123,100–$196,900 / yearThe primary focus of this role is FPGA verification, working closely with cross‑functional teams to deliver high‑quality, robust designs. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.
Senior Digital ASIC Design Engineer The Charles Stark Draper LaboratorySenior Digital ASIC Design EngineerCambridge, MassachusettsDraper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus.
ASIC/FPGA Design Engineer V Lockheed Martin CorpASIC/FPGA Design Engineer VNorth Andover, MA$145,200–$255,990 / yearPay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $145,200 - $255,990. The Silicon Solutions team of Lockheed Martin Space is building the best ASIC/FPGA team in the world, and are seeking a highly talented and motivated ASIC & FPGA Design Engineer who has a passion for microchip design and space.
Staff Engineer, Digital ASIC Design CONTRACT Butterfly Network IncStaff Engineer, Digital ASIC Design CONTRACTBurlington, MAIdeally, you also have these skills/experiences/attributes (but it's ok if you don't!): Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline. Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces.
Staff Engineer, Digital ASIC Design Butterfly Network IncStaff Engineer, Digital ASIC DesignBurlington, MABaseline skills/experiences/attributes: • BS/MS/PhD in EE/CE (or equivalent practical silicon design experience) • 8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle • Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support • Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces • Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations • Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs • Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb) • Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking • Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes • Strong cross-functional communication to close hardware-firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders. These include: • Adhering to all company security policies and procedures • Utilizing provided company assets securely • Completing all required security awareness training programs • Safeguarding company data and systems from unauthorized access, modification, or destruction • Contributing to the overall security posture of the organization • Immediately reporting any suspected or actual security incidents, including phishing attempts, malware infections, or unauthorized access, following the established incident response procedure.
ASIC & FPGA Design Engineer Senior Staff Lockheed Martin CorpASIC & FPGA Design Engineer Senior StaffMA$145,200–$255,990 / yearAs the ASIC & FPGA Design Engineer you will own the full life cycle of complex FPGA solutions-from initial specification through production release-while mentoring teammates and collaborating with software, hardware, and systems engineers to turn system concepts into field ready hardware. Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $145,200 - $255,990.
ASIC Design Verification Engineer Broadcom IncASIC Design Verification EngineerMA$129,400–$207,000 / yearWe are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Distinguished Technologist, ASIC Design Architect Hewlett Packard Enterprise CoDistinguished Technologist, ASIC Design ArchitectWestford, MA$183,000–$365,000 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We are seeking an experienced ASIC Design Architect to own the hardware architecture, microarchitecture, and successful delivery of complex ASICs from concept through tape‑out and silicon bring‑up.
ASIC and Logic Design Engineering Manager (Teradyne, North Reading) Teradyne IncASIC and Logic Design Engineering Manager (Teradyne, North Reading)MA$4–$6 / hourRequires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed signal ASIC design, circuit board design, software and systems engineering to specify and implement new products. Opportunity Overview The Logic Design Manager is responsible for leading a team of developers in designing and verifying FPGAs for Teradyne Compute Test Divisions next generation products.
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA) TeradyneAdvanced ASIC Physical Design Lead (Teradyne, North Reading, MA)North Reading, MA$192,300–$307,600 / yearIn this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. ATTENTION APPLICANTS WITH DISABILITIES: If you’re unable to access our on-line application due to a disability you may visit one of our locations or our Corporate Office at 600 Riverpark Drive, North Reading, MA and request a paper application form.
Distinguished Engineer, ASIC (CONTRACT) Butterfly NetworkDistinguished Engineer, ASIC (CONTRACT)Boston, MAComfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts). Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces.
Distinguished Engineer, Digital ASIC Butterfly NetworkDistinguished Engineer, Digital ASICBoston, MAComfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts). In addition to its medical imaging products, Butterfly Embedded is the Company's Ultrasound-on-Chip licensing and co-development program designed to enable a new wave of ultrasound-enabled technologies across non-competitive healthcare markets and beyond.
Senior FPGA or ASIC Engineer Mitre CorpSenior FPGA or ASIC EngineerBedford, MA$126,800–$158,500 / yearMinimum qualifications include: Typically requires a minimum of 5 years of related experience with a Bachelor's degree; or 3 years and a Master's degree; or a PhD with relevant experience who can immediately contribute at this job step; or equivalent combination of related education and work experience. Our diverse set of sponsors and research objectives provide a wide variety of interesting work opportunities such as: Real-time communication and sensor systems leveraging cutting-edge FPGA technology and SDR platforms.
Mixed Signal ASIC Engineer Ayo SemiconductorMixed Signal ASIC EngineerBoston, MassachusettsOur photonic processors will provide orders of magnitude improvement in speed and power efficiency in comparison to conventional digital compute platforms by taking advantage of the natural parallelism, speed and energy efficiency of light. Perform schematic capture, layout, and verification for mixed-signal integrated circuits with elements including digital-to-analog converters, analog-to-digital converters, transimpedance amplifiers, and transconductance amplifiers.
Senior/Principal Hardware ASIC Validation Engineer The Charles Stark Draper LaboratorySenior/Principal Hardware ASIC Validation EngineerCambridge, MassachusettsDraper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. • Debug test programs, correlate production test solutions to engineering bench measurements, and transfer production test solutions to manufacturing sites.
Distinguished Engineer, ASIC CONTRACT Butterfly Network IncDistinguished Engineer, ASIC CONTRACTMAComfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware-firmware interfaces (register maps, control/status paths, data-plane contracts). Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces.
Project Lead ASIC Engineer The Charles Stark Draper Laboratory IncProject Lead ASIC EngineerCambridge, MA$95,000–$245,000 / yearDraper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. Job Description Summary: Draper is looking for an energetic, service minded ASIC project leader, who enjoys helping others to succeed by providing team members and clients with motivation and support in a positive and professional work environment.
Senior ASIC Methodology Engineer - LPU Division NVIDIA CorpSenior ASIC Methodology Engineer - LPU DivisionMA$152,000–$241,500 / yearWorking shoulder-to-shoulder with an outstanding ASIC development team, you will invent novel architectures and end-to-end workflows that transcend traditional infrastructure, unlocking new levels of capability across logic design, verification, and physical design. • Identify, curate, and leverage real-time data to enable effective AI models and analytics, working with infrastructure teams to ensure scalable and secure data pipelines.
Senior ASIC Timing Engineer NVIDIASenior ASIC Timing EngineerWestford, MassachusettsNVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
Senior ASIC Verification Engineer, Coherent High Speed Interconnect NVIDIA CorpSenior ASIC Verification Engineer, Coherent High Speed InterconnectWestford, MAAs a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
Senior ASIC Front End Infrastructure Engineer NVIDIA CorpSenior ASIC Front End Infrastructure EngineerWestford, MAThis position offers the opportunity to have a real impact on a dynamic, technology-focused company impacting product lines ranging from consumer graphics to artificial intelligence, self-driving cars, and supercomputers. Rapidly learning and deploying best in class internal and industry solutions including AI harnesses in secure environments that you then use to build Skills and Agents for Infrastructure Automation?
Senior LPU ASIC Engineer NVIDIA CorpSenior LPU ASIC EngineerMACross-Functional Optimization: Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation. Methodology Innovation: Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.
ASIC Design Verification Technical Leader Cisco Systems IncASIC Design Verification Technical LeaderMaynard, MA$189,300–$271,500 / yearIn this role, you will: • Lead and develop detailed and comprehensive test plans • Lead and develop verification test benches • Apply innovative verification techniques to complex designs • Supervise the timely execution of test plans by the rest of the team • Lead and assist with chip-level design tradeoffs by working with design engineers • Participate in the review of design verification coding and coverage metrics • Provide technical leadership & mentoring • Work collaboratively with the team to develop & incorporate the latest test technologies & processes. The role requires someone to demonstrate their experience applying sophisticated verification techniques to ASIC projects: ensuring design quality, leading sophisticated technical projects, developing process improvements for the team, and mentoring teammates on techniques, technology & methods for verification.
ASIC CAD Engineer The Charles Stark Draper LaboratoryASIC CAD EngineerCambridge, MassachusettsDraper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. They enable the use of EDA tools, maintain EDA licenses, install PDK data, support the compute farm, manages revision control systems and assist design teams with tool issues.
Senior FPGA Design Engineer RTXSenior FPGA Design EngineerMassachusettsActive and existing security clearance required after day 1 At RTX, the world's largest aerospace and defense company, 185,000 great minds are united by purpose and inspired to make a difference solving the world’s most complex problems. Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route.
Engineer: Sr. Electrical Design Engineer NanobiosymEngineer: Sr. Electrical Design EngineerCambridge, MAPosition Overview:We are expanding our development team and seeking an exceptional Senior Electrical Design Engineer with a strong background in hardware design, design for manufacturing (DFM), and full product realization. This is a hands-on, technical leadership role for someone passionate about innovation, quality, and building real-world products that make an impact.
Senior Electrical Engineer - FPGA Design RTX CorpSenior Electrical Engineer - FPGA DesignTewksbury, MADesigners work with circuit card designers and systems engineers to develop requirements, architect new parts, collaborative modeling of algorithms, partition and perform code development, simulation, and place and route. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces.
Engineer: Senior Electrical Design Engineer NanobiosymEngineer: Senior Electrical Design EngineerCambridge, MAWe are expanding our development team and seeking an exceptional Senior Electrical Design Engineer with a strong background in hardware design, design for manufacturing (DFM), and full product realization. This is a hands-on, technical leadership role for someone passionate about innovation, quality, and building real-world products that make an impact.
Member of Technical Staff, ASIC Verification NetpremeMember of Technical Staff, ASIC VerificationBoston, MassachusettsDrive effective and seamless collaboration with partner teams across architecture, design, physical design, firmware, DFT, and post silicon domains to ensure successful system level functionality. Interface with external IP vendors, foundries and EDA tool providers to ensure dependencies and roadblocks are addressed in a timely fashion to support team deliverables.
Semiconductor Design Engineer [Teradyne, N. Reading, MA] TeradyneSemiconductor Design Engineer [Teradyne, N. Reading, MA]North Reading, MA$140,500–$224,800 / yearYour work will directly support innovations in advanced compute architectures, chiplet‑based systems, and high‑density interfaces, helping to ensure exceptional performance, accuracy, and reliability across Teradyne’s industry‑leading test platforms. + Development Tools: Cadence(Xcellium), Synopsys(Spyglass CDC/LINT), Xilinx(Vivado), Intel(Quartus), revision control tools(Clearcase, GIT, SVN), bug tracking tools(JIRA or other), continuous integration development methodologies and tools.
Senior Engineer, Digital Design Engineering Analog Devices IncSenior Engineer, Digital Design EngineeringWilmington, MA$124,342–$175,440 / yearRequirements: Must have a Masters degree in Electrical Engineering, Electronic Engineering, Computer Science, Computer Engineering, or closely related technical field (willing to accept foreign education equivalent) and 24 months of experience as a Digital Design Engineer or related occupation performing digital or mixed signal design and verification. Duties: Develop state-of-the-art solutions involving analog, mixed-signal, power, RF, and digital signal processing integrated circuits used in electronic equipment for a wide-range of industries, including healthcare, communications, aerospace and defense, instrumentation, and emerging markets.
Staff Engineer, Design Verification Engineering Analog Devices IncStaff Engineer, Design Verification EngineeringWilmington, MA$171,787–$209,715 / yearRequirements: Must have a Master's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing IC design or validation. In the alternative, a Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and six (6) years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
Principal Program Protection Software Engineer RTXPrincipal Program Protection Software EngineerWoburn, MassachusettsAbility to obtain INTERIM U.S. government issued security clearance is required prior to start date At RTX, the world largest aerospace and defense company, 185,000 great minds are united by purpose and inspired to make a difference solving the world’s most complex problems. As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.
Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus) BAE SystemsSenior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)Nashua, NH$130,355–$221,603 / yearWhile in this job you will + Plan, architect, develop, and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL; + Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions in Electronic Warfare systems; + Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases; + Enhance your leadership skills while leading small to medium sized DV teams + Create reusable Verification IP to be shared across the organization; + Drive changes to our process and methodologies. \#ESFPGA \#IJS **Required Education, Experience, & Skills** + Bachelor's Degree and 8 years work experience (or equivalent experience) + Current Security Clearance (Secret), or eligible to obtain one + Experience planning, architecting, developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record of managing and executing to schedules, and driving tasks to closure.
Staff Engineer, Design Verification Marvell Technology IncStaff Engineer, Design VerificationWestborough, MAThis includes supporting re-architecture efforts for AI-driven workloads, validating system-level performance, and helping identify and resolve architectural bottlenecks in scalable, high-bandwidth, and energy-efficient platforms. Perform deep RTL debugging and root-cause analysis of complex functional and system-level issues, working closely with design and architecture teams to ensure high-quality, testable implementations.
Principal Physical Design Engineer Marvell Technology IncPrincipal Physical Design EngineerWestborough, MABachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree. Strong knowledge of static timing analysis (PrimeTime, Tempus), EM/IR‑drop and crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction tools (Quantus, StarRC), and formal/physical verification tools (Formality, Verplex, Calibre, Hercules).
Senior Staff RTL Design Engineer- 16908 Synopsys IncSenior Staff RTL Design Engineer- 16908MAWe partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.
Software Engineer, Design Automation (Senior / Staff+) Reframe SystemsSoftware Engineer, Design Automation (Senior / Staff+)Boston, MassachusettsWe're looking for a Staff Software Engineer to own the hardest parts of our design automation platform: the system that takes a high-level design and, with minimal intervention, produces a manufacturable model and production plan (think: every stud, nail, HVAC register, and duct placed). Through our vertically integrated delivery model and highly automated microfactories, we deliver climate resilient homes and buildings with greater speed and predictability than traditional construction.
Timing Design Engineer Apple IncTiming Design EngineerWaltham, MAYou will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus) BAE Systems PlcSenior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)Nashua, NH$130,355–$221,603 / yearPlan, architect, develop, and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL; Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions in Electronic Warfare systems; Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases; Enhance your leadership skills while leading small to medium sized DV teams. About BAE Systems Electronic Systems BAE Systems, Inc. is the U.S. subsidiary of BAE Systems plc, an international defense, aerospace and security company which delivers a full range of products and services for air, land and naval forces, as well as advanced electronics, security, information technology solutions and customer support services.