Sr. ASIC Design Engineer, Blink/Ring ASIC Team Ring, Inc (Inactive)Sr. ASIC Design Engineer, Blink/Ring ASIC TeamNorth Reading, MACustomer-Obsessed Engineering: We work backwards from real customer needs to create super-low power, energy-efficient designs featuring the latest advances in AI, video processing, low-power communications, and leading-edge CMOS fabrication technology. ASIC Design Engineer on our Blink/Ring ASIC Team, youll work on leading-edge System-on-Chip (SoC) designs that directly impact customer experiences.
Sr. ASIC Design Engineer, Blink/Ring ASIC Team Amazon.com IncSr. ASIC Design Engineer, Blink/Ring ASIC TeamNorth Reading, MACustomer-Obsessed Engineering: We work backwards from real customer needs to create super-low power, energy-efficient designs featuring the latest advances in AI, video processing, low-power communications, and leading-edge CMOS fabrication technology. If you"re passionate about creating silicon that powers the future of smart home technology and want to work where your innovations directly delight customers, we want to hear from you.
Lead ASIC Design Engineer Mitre CorpLead ASIC Design EngineerBedford, MA$156,400–$195,500 / yearBasic Qualifications: Typically requires a minimum of 8 years of related experience with a Bachelor's degree in electrical engineering, computer engineering, or a related field or 6 years and a Master's degree in electrical engineering, computer engineering, or a related field. With objectivity and integrity at our core, we lead federally funded research and development centers for U.S. government agencies - collaborating with industry and academia to deliver integrated, high-impact solutions that advance our nation's health, security, and prosperity.
ASIC/FPGA RTL Design Engineer Connexion Systems + EngineeringASIC/FPGA RTL Design EngineerBedford, MA$90–$110 / hourDegree Level Bachelor's Degree Yes Design Digital Circuit Design 10 years FPGA Hardware Design (Xilinx Vivado) 10 years Electrical/Electronics Xilinx FPGA 10 years Engineering Experience developing hardware verification plans 10 years Hardware Hardware Design 10 years Programming VHDL / Verilog 10 years Signal Processing ASIC Design 10 years ASIC verification experience 10 years Digital Signal Processing 5 years Software Tools Vivado Software Experience 10 years Nice to Have Degree Level Masters Degree Yes PhD Yes Electrical/Electronics System Verilog UVM 0 years Networks Working with Ethernet/Serdes IP 0 years Programming MATLAB Programming 0 years Scripting Languages: Perl, Python, C/C++ 0 years RF/Microwave Experience in FPGA development for RF systems 0 years Signal Processing FPGA development for Software Defined Radio platforms 0 years The Tactical Networks Group is seeking to hire a hardware engineer with 10 years of experience working on different aspects of ASIC design and FPGA design for a high-throughput, low-power signal processing for a communications applications.
Senior Analog/Mixed Signal ASIC Design Engineer The Charles Stark Draper LaboratorySenior Analog/Mixed Signal ASIC Design EngineerCambridge, MassachusettsTypical responsibilities include creating top level and circuit-level specifications, developing conceptual circuit designs, reviewing detailed block-level designs during implementation, conducting chip level-planning with implementation team, and providing inputs to verification and test planning. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities.
ASIC Design and Verification Engineer - AI Analog DevicesASIC Design and Verification Engineer - AIWilmington, MassachusettsSVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire design verification landscape - including Unified Metric-Driven Verification (MDV), System Verilog (SV)/UVM-based methodologies, Mixed-Signal DV, Post-Silicon Validation Shift-Left, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies. In this role, you will leverage your knowledge in Integrated Circuit (IC) design and verification with working knowledge of AI/ML to develop, integrate, deploy, and support best-in-class Agentic AI solutions including custom instructions, skills and automation scripts.
Lead ASIC Digital Design Engineer General Dynamics CorpLead ASIC Digital Design EngineerSudbury, MA$176,512–$187,000 / yearEducation Requirements: Bachelors degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience. General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation.
Senior ASIC Hardware Design Engineer NVIDIASenior ASIC Hardware Design EngineerWestford, MassachusettsAs a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power GPU and interconnect subsystems. You will work closely with architects, design engineers, verification engineers, and physical design engineers to contribute to the design and development of next-generation NVLink protocol and GPU subsystem logic, delivering functional, performant, and physically implementable designs.
Senior Asic Hardware Design Engineer NvidiaSenior Asic Hardware Design EngineerWestford, MAAs a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power GPU and interconnect subsystems. You will work closely with architects, design engineers, verification engineers, and physical design engineers to contribute to the design and development of next-generation NVLink protocol and GPU subsystem logic, delivering functional, performant, and physically implementable designs.
Asic Design Engineer Broadcom CorporationAsic Design EngineerAndover, MA$127,100–$203,400 / yearJob Description: We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
ASIC Design Engineer Broadcom IncASIC Design EngineerMA$127,100–$203,400 / yearJob Description: We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
SoC/ASIC Design Verification Engineer zeroRISCSoC/ASIC Design Verification EngineerBoston, MassachusettszeroRISC zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers.
Advanced ASIC Physical Design Lead Artech LLCAdvanced ASIC Physical Design LeadNorth Reading, MA$93–$148 / hourIn this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA).
Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU NVIDIASenior ASIC Design Verification Infrastructure and Tools Engineer – GPUWestford, CaliforniaOur high-speed IO infrastructure team develops the flows that keep large-scale ASIC development moving: integration automation, pre-submit qualification, build and verification infrastructure, operational metrics, and debug workflows. Apply practical AI workflows where they build leverage, including debug assistance, run triage, summarization, documentation, and workflow automation.
Senior ASIC Design Verification Infrastructure and Tools Engineer - GPU NVIDIA CorpSenior ASIC Design Verification Infrastructure and Tools Engineer - GPUWestford, MAOur high-speed IO infrastructure team develops the flows that keep large-scale ASIC development moving: integration automation, pre-submit qualification, build and verification infrastructure, operational metrics, and debug workflows. What You'll Be Doing: Apply practical AI workflows where they build leverage, including debug assistance, run triage, summarization, documentation, and workflow automation.
Senior Digital ASIC Design Engineer The Charles Stark Draper LaboratorySenior Digital ASIC Design EngineerCambridge, MassachusettsDraper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. Familiarity with architectures for secure systems design, e.g., cryptographic encoders / decoders or tagged processor architectures is a plus.
Asic Design Verification Engineer Broadcom CorporationAsic Design Verification EngineerAndover, MA$129,400–$207,000 / yearWe are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
ASIC Design Verification Engineer Broadcom IncASIC Design Verification EngineerMA$129,400–$207,000 / yearWe are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Distinguished Technologist, Asic Design Architect Hewlett Packard EnterpriseDistinguished Technologist, Asic Design ArchitectWestford, MA$183,000–$365,000 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
Asic And Logic Design Engineering Manager (Compute Test, North Reading) Teradyne, Inc.Asic And Logic Design Engineering Manager (Compute Test, North Reading)North Reading, MA$4–$6 / hourRequires close collaboration with the other FPGA design and verification managers and with other engineering disciplines including mixed signal ASIC design, circuit board design, software and systems engineering to specify and implement new products. Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release.