Senior Principal Engineer, Offensive Security Astera LabsSenior Principal Engineer, Offensive SecuritySan Jose, CA$190,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Principal Engineer, Security Architect Astera LabsSenior Principal Engineer, Security ArchitectSan Jose, CA$190,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Principal Engineer, Security Architect 2026- 346 Astera Labs IncSenior Principal Engineer, Security Architect 2026- 346San Jose, CA$190,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Principal Engineer, Offensive Security 2026-345 Astera Labs IncSenior Principal Engineer, Offensive Security 2026-345San Jose, CA$190,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Engineer, AI Network Security Google LLCPrincipal Engineer, AI Network SecuritySunnyvale, CAAs the Cloud Networking AI Principal Engineer for Network Security, you will provide strategic direction to Googles Networking Security portfolio, including the development of next-generation security offerings by leveraging AI and autonomous AI agents. Collaborate with senior leaders to ensure Google Cloud Platform (GCP) continues to be the most secure cloud for enterprise applications as they broadly adopt agentic workflows.
Principal Engineer, Infrastructure and Data Center Operations Google LLCPrincipal Engineer, Infrastructure and Data Center OperationsSunnyvale, CAYou will be responsible for driving forward-looking, end-to-end solutions to Google"s significant AI infrastructure challenges, partnering across DCOps and teams across AI2 to ensure operational efficiency, agility, and rigor is baked into our operations and long-term strategy. You will provide technical direction, strategic alignment, and operational guidance, focusing on innovative solutions that drive significant uplift in the performance of our infrastructure and the teams that support it.
Principal Engineer, Signal-Integrity and Power-Integrity SK hynix AmericaPrincipal Engineer, Signal-Integrity and Power-IntegritySan Jose, California$185,000–$220,000 / yearMethodology Development: Invent and propagate best‑practice SIPI methodologies, including electromagnetic extraction, multi‑port S‑parameter modeling, and power‑network analysis for complex packaging environments. Architecture & Design: Lead the creation of high‑performance SiP architectures (HBM, interposer, 3 D stacks) and validate power‑delivery and signal‑integrity across the full stack—from silicon to substrate.
Principal Engineer, AI System Architect (Hardware) Samsung SemiconductorPrincipal Engineer, AI System Architect (Hardware)San Jose, CA$219,000–$351,000 / yearAnalyze representative and emerging system-level architectural research (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung's long-term AI platform strategy.
Principal Engineer, Technology Development Engineering SanDisk CorpPrincipal Engineer, Technology Development EngineeringMilpitas, CAAn employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan.
NewPrincipal Engineer, Product Development Engineering SanDisk CorpPrincipal Engineer, Product Development EngineeringMilpitas, CAAn employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. You will lead cross-functional teams, mentor engineering talent, and champion technical excellence while collaborating closely with design, manufacturing, and quality teams to deliver products that exceed customer expectations.
Principal Engineer, SerDes Validation Ayar LabsPrincipal Engineer, SerDes ValidationSan Jose, CaliforniaDrive Product Bring-up: Collaborate with Design Engineering to bring up cutting-edge silicon photonic and laser products, troubleshooting and resolving complex technical issues on the optical SerDes devices. Lead New Product Introduction (NPI): Collaborate with multi-disciplinary teams to identify and implement product improvements through bench characterization and ensure successful transition of products from development to mass production.
Principal Engineer, Electronic Hardware Design Ayar LabsPrincipal Engineer, Electronic Hardware DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Principal Engineer, SerDes AMS Design and Architecture Ayar LabsPrincipal Engineer, SerDes AMS Design and ArchitectureSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Key Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
Principal Engineer, Hardware Design (AI2518) SiMa Technologies IncPrincipal Engineer, Hardware Design (AI2518)San Jose, CA$203,800–$315,900 / yearThe actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. Expert-level RTL design skills (Verilog/SystemVerilog), with hands-on experience in synthesis, timing closure, and DFT concepts.
Principal Engineer, AI & ML Design Verification (AI2517) SiMa Technologies IncPrincipal Engineer, AI & ML Design Verification (AI2517)San Jose, CA$203,800–$315,900 / yearRequired Background: BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs. Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc. ) from scratch along with usage know how of debug & coverage tools.
Principal Engineer, SOC Design Samsung SemiconductorPrincipal Engineer, SOC DesignSan Jose, CA$219,000–$351,000 / yearBachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing.
Principal Engineer, Silicon Validation Ayar Labs IncPrincipal Engineer, Silicon ValidationSan Jose, CA$200,000–$255,000 / yearBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Root Cause and Debug: Investigate and drive to closure all silicon failure modes, from signal integrity issues to mixed-signal anomalies, using systematic debug methodologies and close collaboration with design and firmware teams.
Principal Electrical Engineer, NA Vantage Data CentersPrincipal Electrical Engineer, NASanta Clara, CA$185,000–$195,000 / yearDeveloping and operating across North America, EMEA and Asia Pacific, Vantage has evolved data center design in innovative ways to deliver dramatic gains in reliability, efficiency and sustainability in flexible environments that can scale as quickly as the market demands. Coordinate heavily with internal engineering teams across all disciplines to ensure products delivered to Operations are streamlined and optimized to meet the needs of the business across all functions.
Senior Principal Engineer -Hardware Signal Integrity & Power Integrity Fox Point RecruitmentSenior Principal Engineer -Hardware Signal Integrity & Power IntegritySanta Clara, CaliforniaAs the Senior Principal Engineer for Signal Integrity (SI) and Power Integrity (PI) , you will serve as the senior technical authority responsible for ensuring that customer platforms built on our Ethernet Switch and UALink silicon meet the highest performance and quality thresholds — from first prototype through mass-production deployment. Compliance & Lab Debug: Lead lab characterization and compliance testing (BER/SER, eye-opening margins, jitter, return loss, crosstalk) using VNAs, BERTs, scopes, TDR, and jitter analyzers.
Sr Principal Engineer, Application Engineering & System Design Fox Point RecruitmentSr Principal Engineer, Application Engineering & System DesignSanta Clara, CaliforniaYour primary mission is to ensure that customers’ next-generation switches, AI fabric platforms, and networking systems are designed right the first time—performant, manufacturable, reliable, and ready for high-volume production. Develop and deliver high-impact technical training to customers and internal teams covering proprietary silicon, reference designs, high-speed design best practices, and productization methodologies.