Design Verification Engineer - Machine Learning Accelerators Meta Platforms IncDesign Verification Engineer - Machine Learning AcceleratorsSunnyvale, CAWork with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading Machine Learning IP's optimized for Mixed Reality and Smart Devices and use-cases, defining verification methodologies for each of the different core IPs Define, track, and lead the execution of detailed test plans for the different modules and top levels Implement scalable test benches including checkers, reference models, assertions in System Verilog Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring design quality targets are met across pre- and post-Silicon product lifecycle Support hand-off and integration of developed subsystems/IP blocks into larger SOC environments Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry10+ years of hands-on experience in SystemVerilog/UVM methodology and C/C++ based verification 10+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Track record of 'first-pass success' in ASIC development cycles Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Masters in Electrical Engineering or Computer Science 5+ years of experience with Design verification/validation of machine learning applications and accelerators 5+ years of experience with Software/Hardware Co-design at firmware, ISA, and application level 5+ years of experience with low power design 5+ years of experience in verification of numerical compute based designs Experience with revision control systems like Mercurial(Hg), Git FPGA/emulation debug experienceMeta builds technologies that help people connect, find communities, and grow businesses. As a Design Verification Engineer at Meta's Reality Labs, you will work with a multidisciplinary group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art machine learning algorithms.
Vice President, Creative Design and Brand Storytelling Williams Sonoma IncVice President, Creative Design and Brand StorytellingSan Francisco, CAEvery season, our Creative team develops immersive stories, compelling campaigns and elevated brand experiences that come to life across digital, retail, catalog, social, packaging and emerging channels. The Vice President of Creative Design & Brand Storytelling leads the creative strategy and execution for all graphic design, brand design systems, copywriting and customer-facing storytelling across Pottery Barn.
Visual Design Director Nutanix Inc.Visual Design DirectorSan Jose, CA$243,000–$486,000 / yearIn locations where our workplace policy applies (i.e. San Jose, Durham, Mexico City, Bangalore, Pune, Hoofddorp, Belgrade, Barcelona, Singapore, Sydney and Tokyo), employees are expected to work onsite a minimum of 3 days per week to foster collaboration, team alignment, and access to in-office resources. If so, you will want to join our dynamic User Experience Design organization at Nutanix, where you'll have the opportunity to define the visual aesthetic of our product portfolio and inspire a talented team to transform complex technical concepts into beautifully intuitive digital experiences.
RTL/Logic Design Engineer Advanced Micro Devices, IncRTL/Logic Design EngineerSanta Clara, CaliforniaWith experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting HBM and GDDR DRAM Technologies.
NewManager, Creative Design Clark Construction Group LLCManager, Creative DesignSan Francisco, CA$90,000–$110,000 / yearAdditional benefits include life insurance, commuter benefit, short & long term disability, fitness reimbursement, FSA, tuition reimbursement, back-up daycare, tutoring & family support benefits, EAP/Work-Life assistance, and a holiday contribution program. Collaborative Design Support: Partner with pursuit teams, operational leaders, and marketing staff to provide creative guidance and hands-on design support for large-scale, complicated efforts.
Senior Design Verification CAD Engineer, Silicon, Google Cloud Google LLCSenior Design Verification CAD Engineer, Silicon, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Engineering - FPGA Design/Verification Engineer The Structures Company, LLCEngineering - FPGA Design/Verification EngineerSunnyvale, CACross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms.
Sr. Staff Engineer, Analog/Mixed-Signal Design Ayar Labs IncSr. Staff Engineer, Analog/Mixed-Signal DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others.
Sr. UX Designer, Shopping Design Amazon.com IncSr. UX Designer, Shopping DesignSan Francisco, CAFrom inception through launch, you will be a design owner, responsible for delivering ambitious concepts and using data to iterate and improve - translating needs and constraints into simple, intuitive, customer-focused solutions. You will drive that vision into solid design deliverables, including multi-modal user interface designs and frameworks for voice and screen, interaction models, design specs, and prototypes.
Senior System Engineer Apple IncSenior System EngineerCupertino, CAContribute to core compositing infrastructure across multiple technical areas of the team Work on performance optimization including frame scheduling and display synchronization across iOS, macOS, tvOS, and watchOS Design and implement compositing features that balance visual quality, battery life, and hardware capabilities Build system features that ensure security and privacy for users Work on input handling and event processing systems Maintain and evolve critical system code, balancing modernization with stability and compatibility Drive technical decisions on complex cross-platform compositing challenges Work with new hardware capabilities including advanced display technologies Identify and resolve compositing issues across the codebase through systematic debugging and root cause analysis Collaborate with GPU driver teams, Display teams, and Metal framework engineers Navigate seamlessly between different Apple platform codebases and technical domains Champion clean, maintainable solutions and contribute to knowledge transfer initiatives Mentor junior engineers and provide technical guidance across compositing areas5+ years of experience in software development with strong systems programming background Deep familiarity with Unix environments, system programming, and low-level debugging Proficiency in C/C++ with understanding of memory management, threading, and performance optimization Strong debugging skills with ability to trace complex issues through multiple layers of abstraction using tools like lldb, dtrace, and Instruments Experience with performance analysis and optimizations. Understanding of compositing, frame timing, vsync, and display technologies Proven track record of leading technical initiatives and driving projects from concept to completion Demonstrated ability to work across multiple technical domains and context-switch effectively Self-driven approach to testing, validation, and ensuring code quality Demonstrated ability to mentor others and provide technical leadership Bachelors or Masters degree or equivalent in Computer Science or related fieldExperience with compositing systems, scheduler design, or graphics infrastructure Experience with GPU Programming, Metal, or modern graphics APIs Familiarity with advanced display technologies and variable refresh rate systems Understanding of display hardware and GPU architectures Experience with event-driven systems and input handling Experience working with large legacy codebases and incremental modernization strategies Experience working across multiple Apple platforms (iOS, macOS, tvOS, watchOS) Experience integrating software with hardware capabilities Proven ability to define processes and drive automation to increase productivity Experience shipping consumer products at scale and working across hardware and software Versatility to work across different technical areas and problem domains.
Principal Mixed Signal RTL Design Engineer TYLsemiPrincipal Mixed Signal RTL Design EngineerSan Jose, CaliforniaDesign and implement supporting digital blocks: ADC interface, DPWM (digital PWM), Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting. Prior experience designing digital controllers for integrated voltage regulators (IVRs) , point-of-load (PoL) converters, or high-current AI/HPC power delivery.
NewSoftware Engineer, Silicon Design Methodology OpenAISoftware Engineer, Silicon Design MethodologySan Francisco, CaliforniaFor unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence.
NewSenior Design Verification Engineer MythicSenior Design Verification EngineerPalo Alto, CA$120,000–$225,000 / yearDesign Verification at Mythic: At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently.
NewSenior RTL Design Engineer, TPU Google LLCSenior RTL Design Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewStaff CAD Engineer, Silicon Design Environment, Google Cloud Google LLCStaff CAD Engineer, Silicon Design Environment, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
TPU SoC Design Engineer, Google Cloud Google LLCTPU SoC Design Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Director, SoC Design Engineering Intel CorpDirector, SoC Design EngineeringSanta Clara, CA$220,920–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). As a trusted domain expert, you will directly influence Intel's technical direction, mentor the next generation of engineers, and drive innovation that strengthens Intel's leadership in the semiconductor industry.
Director, Soc Design Engineering Intel Corp.Director, Soc Design EngineeringSanta Clara, CA$220,920–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). As a trusted domain expert, you will directly influence Intel's technical direction, mentor the next generation of engineers, and drive innovation that strengthens Intel's leadership in the semiconductor industry.
Director, Silicon Design Engineering Intel Corp.Director, Silicon Design EngineeringSanta Clara, CA$220,920–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Generate and validate timing constraints and address timing violations at the chip and block levels for SoCs.- Conduct timing rollups and ensure functionality of designs with optimized performance and power characteristics.-
Design Verification Lead Advanced Micro Devices, IncDesign Verification LeadSan Jose, CaliforniaAs a member of the front-end design and integration team, you will collaborate closely with architecture, IP design, physical design, firmware, and product engineering teams to deliver first-pass silicon success for next-generation PCIe and CXL-based IP solutions. KEY RESPONSIBILITIES: Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.