Digital design expertise (state machines, data paths, FIFOs, asynchronous crossings, clock and reset concepts, high-speed and low-power design) using Verilog/SystemVerilog and synthesizable design concepts targeting deep sub-micron nodes, with a comprehensive understanding of architectural impact on logic synthesis, timing closure, and physical implementation. The ideal candidate brings deep expertise in computing and communication systems -including memory subsystems, inter- and intra-chip interconnects, Ethernet, CXL, PCIe, UCIe, and UALink - and understands how these technologies support scalable AI infrastructure across accelerator, chiplet, and data center environments.