High Speed Digital Design Engineer Tesla IncHigh Speed Digital Design EngineerPalo Alto, CA$100,000–$228,000 / yearThe Energy Electrical Engineering team designs the eyes, ears, and brains of Tesla's Vehicle charging & Optimus charging and residential/industrial energy storage products including Powerwall and Megapack. You ll design high-bandwidth data acquisition systems, real-time control processors with multi-gigabit interfaces, signal integrity-critical PCBs, and the digital backbones.
NewSocial Media & Content Lead Rhoda AISocial Media & Content LeadMountain View, CaliforniaOur robots are designed to be generalists capable of operating in complex, real-world environments and handling long-tail edge cases, made possible by our cutting edge research and end-to-end system design. You’ll work directly with our researchers, engineers, and leadership to turn cutting-edge research, robot demos, product milestones, and company news into compelling content for the AI, robotics, and broader technology communities.
RTL Design & Integration Engineer Advanced Micro Devices IncRTL Design & Integration EngineerSan Jose, CAYou will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting PPA, cost and schedule optimized Silicon implementation and first-time-right SW solution. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward.
Senior Fpga Design Engineer (Mtd, San Jose, CA) Teradyne, Inc.Senior Fpga Design Engineer (Mtd, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Design Verification Engineer- CPU AuradineDesign Verification Engineer- CPUSanta Clara, CA$200,000–$300,000 / yearYou will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads. We are designing a leading edge, high performance processor from scratch, and you will own a functional domain of its verification from test plan through coverage closure, proving that a newly designed microarchitecture behaves as intended.
Senior Design Engineer (MOSFET / IGBT) Alpha & Omega SemiconductorSenior Design Engineer (MOSFET / IGBT)Sunnyvale, CAFull timeAt Alpha and Omega Semiconductor (AOS), we design, develop and globally supply a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM, TVS, GaN/SiC, Power IC and Digital Power products. Primary job functions include:Power device structure and process simulation with TCAD tools including Tsuprem4, Medici, and SentaurusDevice characterization with LCR meter, curve tracer, FET test, etc.
RTL2GDS IC Sr. Principal Design Engineer Cadence Design Systems IncRTL2GDS IC Sr. Principal Design EngineerSan Jose, CA$161,000–$299,000 / yearProvide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff. The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology.
Physical Design CPU Methodology Engineer Tenstorrent IncPhysical Design CPU Methodology EngineerSanta Clara, CAThis role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA outcomes, and scalable methodology adoption across multiple projects and teams. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
SerDes RTL Design Engineer Advanced Micro Devices, IncSerDes RTL Design EngineerSan Jose, CaliforniaAMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.
Principal Design Engineer DustPhotonics LtdPrincipal Design EngineerSan Jose, CA$180,000–$250,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products.
Sr. Staff/Principal Engineer, Digital Design (San Diego) InnoPhase IoTSr. Staff/Principal Engineer, Digital Design (San Diego)San Jose, CAIf you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you'll find your playground at Innophase IoT. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc.
Senior Principal Digital Design Engineer CadenceSenior Principal Digital Design EngineerSan Jose, CA$154,000–$286,000 / yearThis role is a highly collaborative individual-contributor position that requires strong RTL design and verification expertise, excellent debugging skills, and the ability to work directly with internal and external customers on complex emulation, simulation, and verification challenges. You will combine deep RTL and verification expertise with strong debugging, communication, planning, and collaboration skills to solve challenging problems and help advance the quality and capabilities of the overall memory IP portfolio.
Fpga Design Engineer (Mtd, San Jose, CA) Teradyne, Inc.Fpga Design Engineer (Mtd, San Jose, CA)San Jose, CA$135,400–$216,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior FPGA Design Engineer (MTD, San Jose, CA) Teradyne IncSenior FPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior Principal Digital Design Engineer Astera LabsSenior Principal Digital Design EngineerSan Jose, CA$205,000–$255,000 / yearThis is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
SoC Design Engineer OmnivisionSoC Design EngineerSanta Clara, California$110,600–$140,000 / yearFamiliar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
Principal Digital Design Engineer Astera LabsPrincipal Digital Design EngineerSan Jose, CA$185,000–$230,000 / yearYou'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principal Power and Board Design Engineer Astera LabsPrincipal Power and Board Design EngineerSan Jose, CA$209,000–$230,000 / yearWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable.
Principal Digital Design Engineer (AI Fabric) Astera LabsPrincipal Digital Design Engineer (AI Fabric)San Jose, CA$185,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Power And Board Design Engineer Astera LabsPrincipal Power And Board Design EngineerSan Jose, CA$209,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.