Lead Analog Serdes Architect/Design Engineer Intel Corp.Lead Analog Serdes Architect/Design EngineerSanta Clara, CA$220,920–$311,890 / yearThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership.
NewMarketing & Pursuits Manager - Sausalito SWA GroupMarketing & Pursuits Manager - SausalitoSausalito, CA$90,000–$115,000Interested applicants should be able to demonstrate strong graphic/communication skills and experience preparing RFQ/RFP responses using desktop publishing software (e.g., Adobe Creative Suite, MS Office, etc.). Minimum 3+ years of experience with marketing and proposal coordination within the Architecture, Engineering, Construction (AEC), Planning, or Landscape Architecture industry; Local candidates preferred.
NewSenior RTL Design Engineer, TPU Google LLCSenior RTL Design Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewSenior Design Verification Engineer MythicSenior Design Verification EngineerPalo Alto, CA$120,000–$225,000 / yearDesign Verification at Mythic: At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently.
Senior Staff Engineer, TPU Co-Design Google LLCSenior Staff Engineer, TPU Co-DesignSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving team behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects Google LLCSenior TPU RTL Design Engineer, Networking, Inter-Chip InterconnectsSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Join the team designing and developing the core components of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
TPU SoC Design Engineer, Google Cloud Google LLCTPU SoC Design Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
ASIC Design Verification Technical Lead, TPU Google LLCASIC Design Verification Technical Lead, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewStaff CAD Engineer, Silicon Design Environment, Google Cloud Google LLCStaff CAD Engineer, Silicon Design Environment, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Physical Design Lead, ASIC Google LLCPhysical Design Lead, ASICSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
RTL Design Engineer, TPU Google LLCRTL Design Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving channel behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Design Technology Co-Optimization Engineer Google LLCDesign Technology Co-Optimization EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Systems Design Engineer, Digital Signal Processing Google LLCSystems Design Engineer, Digital Signal ProcessingSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Principal Mixed Signal RTL Design Engineer TYLsemiPrincipal Mixed Signal RTL Design EngineerSan Jose, CaliforniaDesign and implement supporting digital blocks: ADC interface, DPWM (digital PWM), Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting. Prior experience designing digital controllers for integrated voltage regulators (IVRs) , point-of-load (PoL) converters, or high-current AI/HPC power delivery.
TPU SoC Design Engineer, Cloud Google LLCTPU SoC Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs, as this is a highly cross-functional and central role that will require interactions with numerous ASIC development teams.
NewSoftware Engineer, Silicon Design Methodology OpenAISoftware Engineer, Silicon Design MethodologySan Francisco, CaliforniaFor unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. We’re looking for a software engineer to help build the design methodology, software abstractions, and infrastructure that enable a small silicon team to develop complex chips rapidly and with high confidence.
Sr. Design Verification Engineer Credo Semiconductor, Inc.Sr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Sr. Design Verification Engineer DustPhotonics LtdSr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
NewCore Engineering - Design Engineer III Artech LLCCore Engineering - Design Engineer IIISunnyvale, CA$80–$86.66 / hourPerform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feedback to design/power-modeling teams. We are seeking a Power Measurement Design Verification Engineer to develop and execute DV test strategies focused on power and performance characterization at the IP and SoC level.
Designer III, Interior Architecture & Design Ware MalcombDesigner III, Interior Architecture & DesignCAEstablished in 1972, Ware Malcomb is a dynamic, forward-thinking commercial real estate design firm providing professional architecture, interior design, civil engineering, branding, building measurement, structural engineering and MEP engineering services to clients throughout the world. You will support project execution through Design Development (DD), Construction Documents (CD), and Contract Administration (CA), including submittals and furniture selection, while mentoring junior team members and coordinating project efforts under the general direction of a licensed interior designer.