Physical Design Engineer Etched.ai IncPhysical Design EngineerSan Jose, CARequirements You may be a good fit if you have: 5-10+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on advanced process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.) Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Deeply creative and able to think from first principles Strong candidates may also have experience with: Familiarity with transformer models and machine learning Ability to program with Python or another scripting language Familiarity with AI tools for programming/coding Startup experience or comfort working in fast-paced environments. Key Responsibilities Deeply understand what is involved in physical design Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure Collaborate with RTL Designers and provide Physical Design feedback to improve PPA Drive dashboards that show the convergence of projects related to PDDepositimize tool flows, working with EDA vendors to incorporate the latest features Accountable for block level closure Supervise the outsourcing of physical design to a 3rd party service.
RTL Design and Integration Engineer, TPU and ML GoogleRTL Design and Integration Engineer, TPU and MLSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. In this role, you will join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters.
Staff Software Engineer, GDC Enterprise Application Platform GoogleStaff Software Engineer, GDC Enterprise Application PlatformSunnyvale, CAWe're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. 5 years of experience building and developing large-scale infrastructure, distributed systems or networks, or experience with compute technologies, storage, or hardware architecture.
Software Engineer, GPU Design Automation NVIDIA CorpSoftware Engineer, GPU Design AutomationSanta Clara, CAThe base salary range is 152,000 USD - 241,500 USD for Level 3, and 184,000 USD - 287,500 USD for Level 4. You will also be eligible for equity and benefits. You'll apply modern software engineering techniques, including AI-assisted development, to a hardware domain where these practices can have outsized impact, and help spread those ways of working across a broader team.
Staff / Senior Staff Physical Design Engineer Bolt GraphicsStaff / Senior Staff Physical Design EngineerSunnyvale, CaliforniaBolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. Drive timing closure (setup/hold) across multiple PVT corners using advanced STA methodologies (OCV/POCV).
Software R&D Engineer, Vlsi Physical Design - New College Grad 2026 NvidiaSoftware R&D Engineer, Vlsi Physical Design - New College Grad 2026Santa Clara, CAWhat you'll be doing: Invent new optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. We as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.
Graphic Designer AI FactoryGraphic DesignerSan Francisco, CAYou'll develop visually striking materials - from decks and one-pagers to event signage and social assets - while ensuring every touchpoint aligns with our brand and product's look and feel. Create clear, visually compelling communications - announcements, reports, email graphics -that resonate with both internal and external audiences.
NewSenior Manufacturing and System Co-Design Workflow Engineer NVIDIA CorpSenior Manufacturing and System Co-Design Workflow EngineerSanta Clara, CAProduction Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs, ATE, SLT, BLT, L10+, before silicon exposes the discrepancy. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready harness: CLIs, MCPs, bug and spec retrieval, human-in-the-loop checkpoints, and evaluation-based CI gates running against real silicon workflows.
HSIO Validation Lead - Silicon Co-Design NVIDIA CorpHSIO Validation Lead - Silicon Co-DesignSanta Clara, CAWhat you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities.
DMTS Design Engineer Micron Technology IncDMTS Design EngineerSan Jose, CA$237,000–$416,000 / yearDepartment Overview: DRAM Engineering (DRAM Memory) focuses on designing and developing Micron's industry leading dynamic random access memory products. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Hsio Validation Lead - Silicon Co-Design NvidiaHsio Validation Lead - Silicon Co-DesignSanta Clara, CAWhat you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities.
Senior Design Verification Engineer MicrosoftSenior Design Verification EngineerMountain View, CA$119,800–$234,700 / yearDoctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. To achieve this goal, the AI Silicon Engineering (AISiE) SoC Design Verification team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.
Principal Silicon Design Subsystem Lead MicrosoftPrincipal Silicon Design Subsystem LeadMountain View, CA$142,800–$274,800 / yearDoctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. To achieve this goal, the Artificial Intelligence System on Chip (AISoC) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.
Visual Designer Pinnacle Technical ResourcesVisual DesignerCupertino, California$60–$62 / hourContractorThe specific compensation for this position will be determined by a number of factors, including the scope, complexity and location of the role as well as the cost of labor in the market; the skills, education, training, credentials and experience of the candidate; and other conditions of employment. The ideal candidate will have a strong passion for design, a keen eye for detail, and the ability to create visually compelling designs that align with project goals and brand identity.
Software Engineer V Pinnacle Technical ResourcesSoftware Engineer VCupertino,, California$120–$130 / hourContractorThe specific compensation for this position will be determined by a number of factors, including the scope, complexity and location of the role as well as the cost of labor in the market; the skills, education, training, credentials and experience of the candidate; and other conditions of employment. Client is seeking an enthusiastic software engineer to help design, implement, and optimize new animations for our custom animation rendering engine.
Communications Operations Manager - Contract TalentBurst, Inc.Communications Operations Manager - ContractSouth San Francisco, CA$54–$58.84 / hourLead event and engagement logistics: Plan and execute logistics for internal engagement activities such as town halls, leader office hours, coffee chats, and functional events, partnering closely with administrative professionals and events teams as needed. Strengthen cross-functional coordination: Partner closely with communications colleagues and stakeholders across the organization - including administrative professionals, events management, and other operational teams - to deliver a seamless experience.
Microsoft Consumer Marketing - Creative Director (Art Director) MicrosoftMicrosoft Consumer Marketing - Creative Director (Art Director)Mountain View, CA$142,800–$274,800 / yearMicrosoft Consumer Marketing is seeking a highly conceptual, craft-driven Microsoft Consumer Marketing – Creative Director (Art Director) with a thorough art direction background to shape the next generation of consumer storytelling and digital experiences across Microsoft’s consumer portfolio including Copilot, Surface, Windows, Microsoft 365, and emerging AI experiences. They should know how to simplify complexity, sharpen narratives, and create modern, premium creative systems that scale across launch moments, product storytelling, social, web, retail, demos, partnerships, and executive communications spanning Copilot, Surface, Windows, Microsoft 365, and future consumer experiences.
New["Part-Time Graphic Design Instructor (Pool)","Part-Time Graphic Design Instructor (Pool)"] West Valley["Part-Time Graphic Design Instructor (Pool)","Part-Time Graphic Design Instructor (Pool)"]Saratoga$36,191–$52,297 / yearEducation & Experience – Possess one of the following: Any bachelor's degree AND two years of graphic design, or related, professional experience; OR Any associate's degree AND six years of graphic design, or related, professional experience; OR A valid California Community College Instructor's Credential in the discipline; OR The equivalent of the above. Assignment - Teaching assignments are available in multiple areas, including Graphic Design, Web Design, Web Development, 3D Animation, Video Production and Editing, Interface Design, User Experience Design, and more.
Manager, Graphics Design VisaManager, Graphics DesignSan Francisco, california$129,200–$206,700 / yearThis role sits at the intersection of design, storytelling, and marketing-working directly with marketing, Account Executives (AEs), sales leaders, and cross‑functional partners to turn ideas into compelling marketing materials that influence executive decisions and win business. The ideal candidate is a self-directed, highly collaborative designer who communicates confidently with MS and sales leaders and owns work end-to-end, raising the bar on the quality and clarity of pitch narratives.
Senior Property Marketing Graphic Designer CBRE Group IncSenior Property Marketing Graphic DesignerSan Francisco, CACBRE serves clients through four business segments: Advisory (leasing, sales, debt origination, mortgage serving, valuations); Building Operations & Experience (facilities management, property management, flex space & experience); Project Management (program management, project management, cost consulting); Real Estate Investments (investment management, development). Atlanta - Georgia - United States of America, Chicago - Illinois - United States of America, Denver - Colorado - United States of America, San Francisco - California - United States of America, Seattle - Washington - United States of America, Washington, D.C. - District of Columbia - United States of America.