PD - Sr Staff - CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology | Eliyan CorporationPD - Sr Staff - CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |CALead methodology and execution for low-power core design targeting aggressive PPA targets in accelerator product lines covering power intent definition, multi-voltage domain management, and clock gating strategy. Define and own comprehensive clocking methodology covering Clock Mesh, Spine-and-Rib, H-Tree, and hybrid topologies selecting the optimal strategy per design class, frequency target, and power budget.
RTL Design Engineer, Machine Learning Accelerators Google LLCRTL Design Engineer, Machine Learning AcceleratorsSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Careers Skip navigation links home Home Homework_outlinework_outline Jobs noogler_hat Students google How we work handyman How we hire person_outline Your career help_outline Help link feedback Send feedback more_vert Help Send Feedback Sign in.
Senior Design Verification Engineer Google LLCSenior Design Verification EngineerMountain View, CAApplyshare linkCopy linkemailEmail a friendMinimum qualificationsBachelors degree in Electrical Engineering Computer Engineering Computer Science a related field or equivalent practical experience.8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with different verification techniques and methodologies including formal GLS UPF based Power simulations UVM and C based testing etc. to achieve bug-free Silicon in complex SoCs.
Senior RTL Design Engineer MythicSenior RTL Design EngineerPalo Alto, CA$120,000–$225,000 / yearWe've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply both creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness.
RTL Design Engineer MythicRTL Design EngineerPalo Alto, CA$120,000–$225,000 / yearWe're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
ASIC Engineer, Design Meta Platforms IncASIC Engineer, DesignSunnyvale, CABachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design Microarchitecture, RTL coding, SoC integration and micro-architecture development Demonstrated communication and collaboration skills Master's or PhD degree in Electrical Engineering, Computer Science or related areas Experience in CPU, NOC, Memory, Die-to-die and Peripheral Subsystems Experience with Synthesis, Timing Closure and Formal Verification Methodology Experienced in managing SOC-level boot flow, Silicon Debug architectures and PLL/sequencing clocks and resets within SOC architecturesMeta builds technologies that help people connect, find communities, and grow businesses. You will collaborate with world-class researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
Design Verification Engineer MythicDesign Verification EngineerPalo Alto, CA$120,000–$225,000 / yearBecause today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING GlobalFoundries IncSr Mgr/Dep Director ASIC Digital Design IP ENGINEERINGSanta Clara, CA$167,000–$275,000 / yearThis role provides technical and organizational leadership for a team of digital design engineers, driving architecture implementation, RTL development, integration, verification closure support, and successful silicon execution. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies.
NewSenior Applied Scientist, Superconducting Digital and Cryogenic Control Electronics,Center for Quantum Computing, Physical Design and Simulation, Enabling Technologies Amazon.com IncSenior Applied Scientist, Superconducting Digital and Cryogenic Control Electronics,Center for Quantum Computing, Physical Design and Simulation, Enabling TechnologiesSan Francisco, CAControlling and reading out orders of magnitude more qubits than today"s systems demands rethinking where classical control lives and what technology implements it; you will design and model superconducting digital logic (e.g., single-flux-quantum-family circuits) and related cryogenic electronics, evaluate them against the wiring, power, and thermal budgets of a scaled system, and co-design control approaches with the qubit devices they serve. The Amazon Web Services (AWS) Center for Quantum Computing (CQC) is seeking a Senior Applied Scientist to research and design cryogenic control hardware for large-scale quantum processors, with an emphasis on superconducting digital circuits.
NewASIC Digital Design, Sr Staff Engineer - 18603 Synopsys IncASIC Digital Design, Sr Staff Engineer - 18603Sunnyvale, CAWe partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.
AutoCAD Design/Drafter Auriga CorporationAutoCAD Design/DrafterMilpitas, CAFull timeProven work experience in preparing computer-aided design of drawings and other graphic material for Electrical, Mechanical, Civil, Structural or Architectural designers using AutoCAD, Map 3D, Civil 3D and/or Revit. Auriga’s cliental includes: investor owned and municipal utilities, rail and transit agencies, federal, state and local government agencies, and international public and private sector organizations.
Digital Design Engineer HPDigital Design EngineerSan Francisco, CaliforniaAs a member of the team, you'll have the opportunity to contribute across the digital design process, develop your craft alongside experienced designers and engineers, and help create new interfaces, interactions, and experiences that shape our product roadmap. We’re especially interested in candidates who have experience or demonstrated interest in any of the following areas: High-fidelity prototyping using code or tools such as Origami Studio, SwiftUI, WebGL, JavaScript, or CSS.
Logic Design Engineer Advanced Micro Devices, IncLogic Design EngineerSanta Clara, CaliforniaThe successful candidate will possess excellent analytical and critical thinking skills with strong attention to detail, demonstrate the initiative and ability to independently drive tasks to successful completion, and communicate effectively across teams and stakeholders. They will bring a collaborative, team-first mindset, contribute positively to a fast-paced environment, and have the ability to mentor and guide junior engineers, fostering both technical growth and team success.
Front-End ASIC Design Engineer - [FullTime] (IK) Central Business SolutionsFront-End ASIC Design Engineer - [FullTime] (IK)Milpitas, CaliforniaSkills Required – Micro-architecture at module/sub-system/chip-level; digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings; integration of IPs/modules/sub-systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support. Experience and domain-knowledge in at least 2-3 of these: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine-learning / AI; FPGA.
RTL/Logic Design Engineer Advanced Micro Devices, IncRTL/Logic Design EngineerSanta Clara, CaliforniaWith experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting HBM and GDDR DRAM Technologies.
Design Verification Engineer- AI Accelerator Lead AuradineDesign Verification Engineer- AI Accelerator LeadSanta Clara, CA$200,000–$350,000 / yearYou will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads. Work with architects to understand the intent behind a newly designed microarchitecture and turn it into detailed test and coverage plans, including the criteria that define correctness for numerical hardware.
Design Verification Engineer- CPU AuradineDesign Verification Engineer- CPUSanta Clara, CA$200,000–$350,000 / yearYou will work closely with architects, RTL engineers, software engineers and system teams to establish confidence in the correctness, performance, reliability and safety of the design, from individual RTL blocks through complete hardware and software systems running real workloads. We are designing a leading edge, high performance processor from scratch, and you will own a functional domain of its verification from test plan through coverage closure, proving that a newly designed microarchitecture behaves as intended.
Design Verification Architect Intel Corp.Design Verification ArchitectSanta Clara, CA$164,470–$232,190 / yearCollaborate with architecture and design teams to create random test generation plans, run functional simulations to identify gaps in design specifications, and conduct failure analysis, coverage analysis, and closure. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
RTL Design Engineer, Interconnect & Memory Systems Tesla IncRTL Design Engineer, Interconnect & Memory SystemsPalo Alto, CA$128,000–$414,000 / yearIn this role, you will focus on the critical data path elements of custom ASICs, including Network on Chip (NoC) architectures, DMA engines, memory controllers, Memory Management Units (MMUs), arbiters, and AXI protocol implementations. You will collaborate closely with system architects, verification engineers, physical design teams, and software/firmware developers to deliver high-performance, power-efficient designs that enable massive-scale AI training and inference.
High Speed Digital Design Engineer Tesla IncHigh Speed Digital Design EngineerPalo Alto, CA$100,000–$228,000 / yearThe Energy Electrical Engineering team designs the eyes, ears, and brains of Tesla's Vehicle charging & Optimus charging and residential/industrial energy storage products including Powerwall and Megapack. You ll design high-bandwidth data acquisition systems, real-time control processors with multi-gigabit interfaces, signal integrity-critical PCBs, and the digital backbones.