Familiar with driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon including memory subsystems and interconnects: scale up, scale out, scale across, power management, liquid cooling at rack scale level, deep system level observability & telemetry and dependent impact into Gen AI and LLM level performance/tco/execution KPIs. The intern will analyze how model architecture, inference behavior, memory movement, data-center constraints, and software stacks influence end-to-end customer outcomes, including throughput, latency, time-to-first-token, tokens per second, power consumption, utilization, total cost of ownership, and deployability.