Experience should include bringing up complex digital designs in emulation, debugging emulation builds, migrating simulation tests to emulation, supporting long-running workloads, improving debug visibility, and working with emulation-ready components such as transactors, checkers, memory models, and bus-functional models. Experience with multiple clock domains, reset domains, clock dividers, asynchronous interfaces, CDC/RDC-sensitive logic, firmware interaction, and digital logic that controls or interfaces with analog/mixed-signal blocks is highly desirable.