Lead and coordinate advanced package development activities from package definition (architecture, bump/ball map, substrate stack-up, body size) and design to mass production, including all aspects of high density/high performance interconnects design, thermo-mechanical (warpage, lid/stiffener, thermal), quality, reliability, cost, and yield constraints. Key Responsibilities: Areas of focus and key responsibilities (include, but not limited to): Own package SI/PI hands-on for high-speed interfaces - LPDDR5x/6 DRAM and PCIe Gen5, plus 10G Ethernet and MIPI: chip-package-board co-design, channel and PDN simulation (loss, crosstalk, eye margin, PDN impedance, IR drop), and lab correlation.