The Engineering Manager owns the FPGA discipline end to end — silicon and board selection, RTL (Register-Transfer Level) architecture, verification strategy, timing closure, toolchains, IP (Intellectual Property) licensing, the bring-up lab, and the team that does the work — and partners daily with software engineering, product, certification, QA (Quality Assurance), manufacturing, and supply chain. Select the silicon and the boards — evaluate FPGA families and COTS (Commercial Off-The-Shelf) cards against sustained line rate, fabric and transceiver headroom, PCIe (Peripheral Component Interconnect Express) generation, optical cage compatibility, lead time, and licence cost — and own the vendor relationships that follow.