Experience taking projects from the concept phase, through chip architecture, writing electrical specifications, process technology selection, die size estimation, managing schedules, IC design, layout supervision, layout extraction and verification, DRCs, LVS, LVL, mask and wafer fabrication monitoring, ATE lab correlation, corner lot characterization analysis, hands-on lab evaluation, release to production, yield improvement, and failure analysis support. Key parameters include voltage and current accuracy, load and line transient response, DC gain, bandwidth, phase and gain margin, slew rate, efficiency, offset, PSRR, CMRR, noise, propagation delay, input and output common mode range, supply headroom.