Key Words: Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing. Primary Job Qualifications: We encourage you to apply if you have any of these preferred skills or experiences: In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment.