Principal Analog Mixed-Signal Design Engineer SiTime CorpPrincipal Analog Mixed-Signal Design EngineerSanta Clara, CA$148,320–$203,940 / yearDetailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture. Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release.
Director, Soc Design Engineering Intel Corp.Director, Soc Design EngineeringSanta Clara, CA$220,920–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). As a trusted domain expert, you will directly influence Intel's technical direction, mentor the next generation of engineers, and drive innovation that strengthens Intel's leadership in the semiconductor industry.
Front End Design Verification Engineer Tenstorrent IncFront End Design Verification EngineerSanta Clara, CAYou'll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
Midcore Design Verification Engineer Tenstorrent IncMidcore Design Verification EngineerSanta Clara, CAYou'll work closely with CPU architects, RTL designers, and software engineers to develop verification strategies, build robust test environments, and uncover the corner cases that matter in a modern out-of-order processor. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
Director, SoC Design Engineering Intel CorpDirector, SoC Design EngineeringSanta Clara, CA$220,920–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). As a trusted domain expert, you will directly influence Intel's technical direction, mentor the next generation of engineers, and drive innovation that strengthens Intel's leadership in the semiconductor industry.
Front End Design Verification Engineer TenstorrentFront End Design Verification EngineerSanta Clara, CAYou'll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
Sr. Design Verification Engineer DustPhotonics LtdSr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Design Verification Intern, MS - Summer 2027 MarvellDesign Verification Intern, MS - Summer 2027Santa Clara, CACompleted courses focusing on computer architecture, logic, processor, memory system, Verilog, VLSI, VHDL, UVM, analog, integrated circuit design, digital logic design, SoC/ASIC design, verification principles, signals, system and signal processing. Across all groups, you'll collaborate with your direct team and cross-functional partners (across software, physical design, digital design, and more) to deliver robust, scalable solutions that enable Marvell's leadership in data infrastructure.
Hardware Systems Design & Integration Engineer - AirPods Apple IncHardware Systems Design & Integration Engineer - AirPodsCupertino, CATranslate complex technical trade-offs into clear narratives for cross-functional partners, contract manufacturers, and executive audiences; build alignment and drive decisions, including the hard calls. We are looking for engineers who want to understand how things work, thrive in ambiguity, and lift the teams around them - people who can dig into a hard problem in the lab and then bring the team along on what they learned and where to go next.
SerDes Circuit Design Engineer Apple IncSerDes Circuit Design EngineerCupertino, CAYou will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best-in-class power, performance, and area (PPA). Experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters.
DDR Design Engineer Apple IncDDR Design EngineerCupertino, CAAs a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization.
Design Verification Apple IncDesign VerificationCupertino, CA$150,400–$225,300 / yearYou'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Work with RTL designers and architects to understand and review specifications and architecture and extract features as part of the verification team supporting Apples Display Technologies portfolio for the next-generation of Apple products.
Digital Layout Design Engineer AppleDigital Layout Design EngineerSanta Clara, CAAs a member of the layout team of the microprocessor group, you will be responsible to deliver PDV clean layout, including the following: - Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies. **Minimum Qualifications** + Bachelors degree in relevant field of study plus 3 years of relevant experience **Preferred Qualifications** + We are looking for applicants experience in custom layout design of deep SubMicron CMOS circuits.
ASIC Design Engineer - Neural Engine DMA Apple IncASIC Design Engineer - Neural Engine DMASunnyvale, CAWorking closely with design verification and formal verification teams to ensure functional correctness: reviewing test plans, debugging failures, and ensuring the designs intended behavior is fully exercised. In this front-end design role, your work will include: Writing well-parameterized RTL structured for correct synthesis, clean timing, and low power, along with assertions and cover points that encode design intent and ensure verification completeness.
Senior Design Verification Engineer MythicSenior Design Verification EngineerPalo Alto, CA$120,000–$225,000 / yearDesign Verification at Mythic: At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently.
Design Verification Engineer - Machine Learning Accelerators Meta Platforms IncDesign Verification Engineer - Machine Learning AcceleratorsSunnyvale, CAWork with cross-functional leads, including product managers, systems architects, researchers, and software architects, to develop industry leading Machine Learning IP's optimized for Mixed Reality and Smart Devices and use-cases, defining verification methodologies for each of the different core IPs Define, track, and lead the execution of detailed test plans for the different modules and top levels Implement scalable test benches including checkers, reference models, assertions in System Verilog Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Collaborate with cross-functional teams such as Design, Model, Emulation and Silicon validation teams towards ensuring design quality targets are met across pre- and post-Silicon product lifecycle Support hand-off and integration of developed subsystems/IP blocks into larger SOC environments Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry10+ years of hands-on experience in SystemVerilog/UVM methodology and C/C++ based verification 10+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Track record of 'first-pass success' in ASIC development cycles Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Masters in Electrical Engineering or Computer Science 5+ years of experience with Design verification/validation of machine learning applications and accelerators 5+ years of experience with Software/Hardware Co-design at firmware, ISA, and application level 5+ years of experience with low power design 5+ years of experience in verification of numerical compute based designs Experience with revision control systems like Mercurial(Hg), Git FPGA/emulation debug experienceMeta builds technologies that help people connect, find communities, and grow businesses. As a Design Verification Engineer at Meta's Reality Labs, you will work with a multidisciplinary group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state of the art machine learning algorithms.
Designer III, Interior Architecture & Design Ware MalcombDesigner III, Interior Architecture & DesignCAEstablished in 1972, Ware Malcomb is a dynamic, forward-thinking commercial real estate design firm providing professional architecture, interior design, civil engineering, branding, building measurement, structural engineering and MEP engineering services to clients throughout the world. You will support project execution through Design Development (DD), Construction Documents (CD), and Contract Administration (CA), including submittals and furniture selection, while mentoring junior team members and coordinating project efforts under the general direction of a licensed interior designer.
FPGA Design Engineer Emcore CorporationFPGA Design EngineerConcord, CA$130,000–$185,000 / yearFull timeJob Title/Code: FPGA Design Engineer; Job Code: RD400Department: Engineering Reports To: Engineering Manager Job Type: Full-Time, Exempt Location: Concord, CA (On-Site)Position Summary:EMCORE is seeking an FPGA Design Engineer to lead FPGA-based logic and firmware development for our high-performance inertial sensing systems. You will design, verify, and implement FPGA logic and the firmware that runs alongside it, working closely with hardware, systems, and manufacturing teams to bring designs from first prototype through volume production.
Senior Digital Design Engineer - High-Speed I/O And Photonics NvidiaSenior Digital Design Engineer - High-Speed I/O And PhotonicsSanta Clara, CAWe recently delivered the industry's first 200G MRM-based silicon photonics chip, revolutionizing high-performance networking and enabling the era of Co-Packaged Optics (CPO) for NVIDIA. What You'll Be Doing: While engaged in frontend development, your responsibilities will include working on a wide range of high-speed, powerful DSPs, silicon photonics IPs, and chips.
Manager, Digital Design - Mixed-Signal High-Speed I/O Serdes NvidiaManager, Digital Design - Mixed-Signal High-Speed I/O SerdesSanta Clara, CAAs a Senior Digital Design Manager in our Mixed-Signal High-Speed I/O SerDes group, you'll lead a team working on NVIDIA's latest groundbreaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving. Lead front-end design flows (Lint/CDC/Synthesis/DFT/LEC/STA) and coordinate with back-end teams for successful chip tape-outs.