li>Optimize and debug critical device fabrication modules for high-yield, low-noise transistor performance, with emphasis on gate-recess control, surface preparation, lithographic residue removal, cap-layer etching, device isolation, passivation, plated airbridges, and compatibility of photoresists, seed layers, and plating chemistries with InP HEMT process integration. Develop and execute cleanroom fabrication processes for InP HEMT devices, including electron-beam and optical lithography, gate-recess patterning, III-V wet and dry etching, ohmic/gate/pad metallization, dielectric passivation, airbridge fabrication, electroplated gold interconnects, resist strip/cleaning optimization, and process troubleshooting.